Delay line loop for on-chip clock synthesis with zero skew and 5

Details Delay line loop for on-chip clock synthesis with zero skew and 5 Delay line loop for on-chip clock synthesis with zero skew and 5

1993-02-26

1995-04-25

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327261, H03K 513, H03K 504

Patent

active

054102634

ABSTRACT:
In an integrated circuit for synthesizing a 50% duty cycle internal clock, the internal clock is synchronized with zero phase difference with respect to an external reference clock having a frequency that is equal to, or is a submultiple of, the synthesized internal clock. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference clock duty cycle. Synchronization of the two clocks is achieved by a delay-line-loop using a voltage controlled delay line with a nominal half period delay of the synthesized clock. The 50% duty cycle is achieved by a second control loop that has as its input both the reference and the inverted synthesized clock. This second loop drives the voltage controlled delay line with the synthesized internal clock signal. The integrated circuit clock synthesizer is intended to operate as an integral part of a microprocessor or a peripheral unit operating in a system having a common external reference clock.

REFERENCES:
patent: 4795985 (1989-01-01), Gailbreath
patent: 4807266 (1989-02-01), Taylor
patent: 5097489 (1992-03-01), Tucci
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5216302 (1993-06-01), Tanizawa
patent: 5223755 (1993-06-01), Richley

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