Delay line control system for automatic test equipment

Details Delay line control system for automatic test equipment Delay line control system for automatic test equipment

1987-12-21

1989-06-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 55, 307269, 307590, 371 1, H03K 1700, G06K 504

Patent

active

048375217

ABSTRACT:
A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

REFERENCES:
patent: 4277693 (1981-07-01), Hoekman
patent: 4468624 (1984-08-01), Rehbein et al.
patent: 4488297 (1984-12-01), Vaid
patent: 4564953 (1986-01-01), Werking

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