Delay line circuit providing clock pulse width restoration...

Details Delay line circuit providing clock pulse width restoration... Delay line circuit providing clock pulse width restoration...

2003-03-27

2004-09-07

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S153000

Reexamination Certificate

active

06788119

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to delay lock loops (DLLs). More particularly, the invention relates to a DLL delay line that includes a clock pulse width restoration circuit.
BACKGROUND OF THE INVENTION
Clock signals are used in virtually every digital integrated circuit (IC) and electronic system to control timing. For example, whenever there is a rising edge on a clock signal, all the flip-flops in a circuit might change state. Clearly, the higher the frequency of the clock signal, the faster the circuit operates. Therefore, much attention has been given to achieving the highest possible clock speeds that can be supported by the clock circuitry.
One problem that typically develops when high-frequency clocks are used is the problem of “clock skew”. Clock skew occurs when a clock signal is routed to two or more destinations and, because of varying delays on the clock paths, arrives at the targeted destinations at different times. For example, clock skew can occur when a clock signal is provided to the output pads and also to the internal circuitry of an IC. There might be, for example, a shorter delay in routing the clock signal to the output pads than there is in routing the clock signal to the internal circuitry. In this example, if the internal circuitry is driving the output pads, the clock skew can cause data errors.
A delay lock loop (DLL) is often used to remove clock skew. A DLL corrects the difference in timing between two skewed clock signals by adding a delay to the slower path. The added delay is the additional delay required to give the slower path exactly N clock periods more delay than the faster path, where N is a whole number. Thus, the two active edges arriving at the two target destinations are aligned, with N clock periods of delay between the two clock signals. A DLL typically continuously monitors the relative delay between a feedback clock signal and an input clock signal, adding an additional unit delay to the output clock signal when the feedback clock is too fast and subtracting a unit delay when the feedback clock is too slow.
DLLs typically contain several delay lines. A delay line is a number of delay elements coupled in series. The delay elements in a delay line are generally designed to have delays as nearly identical as possible. Output signals from the delay line are typically tapped after each delay element or each group of delay elements. The number of unit delays added to the input clock signal is determined by which tap signal is selected to provide the DLL output signal.
FIG. 1
shows a known DLL. The DLL of
FIG. 1
includes a phase shifter circuit (clock phase shifter)
101
and two delay circuits A and B (
102
and
103
, respectively), all coupled in series. Each of these elements includes at least one delay line. In the pictured DLL, delay circuit A includes a 256-tap delay line, and delay circuit B includes four 128-tap delay lines
104
a
-
104
d
. Delay circuit A is typically used to control feedback delays, while delay circuit B is used to generate quarter phasing of the input clock CLKIN (hence the four delay lines in delay circuit B).
Delay circuit B can include any number of delay lines having any number of taps. The more delay lines that are included in delay circuit B, the higher the number of clock phases that can be provided by the DLL. For example, when four delay lines are included, quarter phasing is supported by the DLL. When six delay lines are included, one-sixth phasing is supported, and so forth. Additionally, the greater the number of taps included in each delay line, the lower the input clock frequency that can be handled by delay circuit B.
Delay circuits B provides five output signals to an output generator circuit
105
. Signal P
00
is a delayed version of clock signal CLKIN_PS, provided by phase shifter circuit
101
. Signals P
25
, P
50
, P
75
, and P
100
are each shifted an additional quarter phase from clock signal P
00
. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Output generator circuit
105
, selects one of the delay line output signals as the output clock signal CLKOUT for the DLL. The output clock signal CLKOUT drives a clock network
106
, e.g., for the integrated circuit including the DLL. From clock network
106
a feedback clock signal CLKFB feeds back to phase shifter circuit
101
.
Phase shifter circuit
101
can optionally be used to add skew (delay offset) between signals CLKIN and CLKFB by phase shifting signals CLKIN and CLKFB to provide phase shifted signals CLKIN_PS and CLKFB_PS. Phase detector
108
compares the phase of the phase shifted feedback clock signal CLKFB_PS with the phase of the phase shifted input clock signal CLKIN_PS, and reports to the control logic (
107
) which of the two signals is ahead of the other. In response, the control logic instructs delay circuit A to either increase or decrease the amount of delay added to the clock path. Delay circuit A is “locked” when it has achieved phase alignment between signals CLKIN_PS and CLKFB_PS.
Phase Detector
109
compares the phase of signals P
00
and P
100
, and reports to the control logic which signal is ahead of the other. In response, the control logic instruct delay circuit B to either increase or decrease the amount of delay added to the clock path, thereby bringing signals P
00
and P
100
closer and closer to being in phase. Delay circuit B is “locked” when it has achieved phase alignment between P
00
& P
100
. Typically, this locking occurs when the delay through delay circuit B has become equal to the clock period of signal CLKIN. Control logic block
107
accepts input signals from blocks
101
,
102
,
103
,
104
a-d
,
108
, and
109
, and provides output signals to blocks
101
,
102
,
103
,
104
a-d
,
105
,
108
, and
109
.
Each delay line typically includes a series of delay elements providing the tap signals and a multiplexer circuit that selects one of the tap signals as the delay line output signal.
FIG. 2
illustrates an exemplary 128-tap delay line. For example, four delay lines similar to that shown in
FIG. 2
can be used to implement delay circuit B of FIG.
1
. However, typically all delay lines in the DLL use the same basic circuitry, to match performance and facilitate the tuning of the clock signal. The number of delay elements in each delay line can vary widely. Typically, the number of delay elements is selected to be a power of two, i.e., 2{circumflex over ( )}N, where N is an integer. This practice simplifies the multiplexer control logic.
Delay line
104
includes a series of 128 tap delays. Tap delay circuit
201
provides 128 tapped output signals D[
0
-
127
].
FIG. 3
shows one implementation of tap delay circuit
201
, which includes 128 unit delay elements TAP
0
-TAP
127
coupled in series. Each delay element provides one tap output signal.
FIG. 4
shows one implementation of a single unit delay element TAPX, which includes four inverters
402
a
-
402
d
coupled in series. The four inverters typically include transistors of the same size and configuration in each delay element, to equalize as much as possible the delay through each delay element. Many other implementations of a delay line delay element are well known and commonly used.
Returning now to
FIG. 2
, the tap signals are provided to the multiplexer circuit, which in this instance includes four multiplexer stages
202
-
205
and a multiplexer controller circuit
206
. Multiplexer stage
1
is a 4-to-1 multiplexer that accepts 128 input tap signals and selects 32 of the input signals, which are provided to multiplexer stage
2
. Multiplexer stage
2
is another 4-to-1 multiplexer that accepts 32 input tap signals and selects 8 of the signals, which are then provided to multiplexer stage
3
. Multiplexer stage
3
reduces the number of tap signals to two, and the final multiplexer stage selects the one tap signal that is used as the output signal for the delay line.
The selection of tap signals is perfor

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