Delay line circuit

Details Delay line circuit Delay line circuit

2006-02-06

2008-08-26

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S284000, C327S286000

Reexamination Certificate

active

07417478

ABSTRACT:
Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.

REFERENCES:
patent: 6573771 (2003-06-01), Lee et al.
patent: 6774691 (2004-08-01), Han et al.
patent: 6781861 (2004-08-01), Gomm et al.
patent: 6812760 (2004-11-01), Kim et al.
patent: 6847246 (2005-01-01), Kaviani et al.
patent: 6850107 (2005-02-01), Gomm
patent: 6873199 (2005-03-01), Nishimura et al.
patent: 6879200 (2005-04-01), Komura et al.
patent: 6895522 (2005-05-01), Johnson et al.
patent: 7049873 (2006-05-01), Pilo et al.

Affiliated with

Also associated with

Rating

Delay line circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay line circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay line circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4011823