Delay gate circuit

Details Delay gate circuit Delay gate circuit

1979-11-23

1982-12-28

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307584, H03K 17284, H03K 3353

Patent

active

043664008

ABSTRACT:
A delay gate circuit consists of first and second stages which each have two serially connected MOS transistors and of a fifth MOS transistor. The gates of the transistors of the first stage serve as first and second circuit input terminals. The gate of the second transistor of the first stage is connected to the gate of the first transistor of the second stage. An output terminal of the first stage is connected to the gate of the second transistor of the second stage and to the drain of the fifth MOS transistor. An output terminal of the second stage is connected to the gate of the fifth transistor and serves as the output circuit terminal.

REFERENCES:
patent: 3551692 (1970-12-01), Yen
patent: 3628065 (1971-12-01), Hill
patent: 3659286 (1972-04-01), Perkins et al.
patent: 4000413 (1976-12-01), Wong et al.
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4275313 (1981-06-01), Boll et al.
Christopherson, "Fet Hysteresis Circuit", IBM Tech. Discl. Bull., vol. 15, No. 5, pp. 1475-1476, 10/1972.
Hsu, "True, Push-Pull Driver", IBM Tech. Discl. Bull., vol. 19, No. 3, pp. 998-999, 8/1976.

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