Delay failure test circuit

Details Delay failure test circuit Delay failure test circuit

2007-03-14

2009-12-29

Tsai, Carlos S (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C714S726000, C714S727000, C714S731000, C714S742000, C714S730000, C713S501000, C713S502000, C713S503000

Reexamination Certificate

active

07640124

ABSTRACT:
In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

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