Delay equalized Z/2Z ladder for digital to analog conversion

Details Delay equalized Z/2Z ladder for digital to analog conversion Delay equalized Z/2Z ladder for digital to analog conversion

2006-05-09

2006-05-09

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S153000

Reexamination Certificate

active

07042381

ABSTRACT:
A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.

REFERENCES:
patent: 4751497 (1988-06-01), Torii
patent: 4920344 (1990-04-01), Henderson et al.
Seams, Jerry, “R/2R Ladder Networks,” Advanced Film Division, AFD006, Sep. 21, 1998, pp. 1-5.
Vorenkamp, P. et al., “WP 3.3: A 1Gs/s, 10b Digital-to Anaog Converter,” 1994 IEEE International Solid State Circuits Conference, Feb. 16, 1994, pp. 52-53.

Affiliated with

Also associated with

Rating

Delay equalized Z/2Z ladder for digital to analog conversion does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay equalized Z/2Z ladder for digital to analog conversion, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay equalized Z/2Z ladder for digital to analog conversion will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3543837