Delay equalization detector

Details Delay equalization detector Delay equalization detector

1989-08-11

1992-04-14

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375110, 333 18, 455 512, H04B 346

Patent

active

051054396

ABSTRACT:
An improved method for detecting that a facility delay has changed is provided. According to the invention, a facility having a delay that may change is coupled to a transmitter and a receiver. The transmitter is coupled to a first clock that transmits a first signal based on its current reading (the first clock signal) from time to time to the receiver via the facility. The receiver is coupled to a second clock that generates a second signal based on its current reading (the second clock signal) responsive to receiving the first clock signal. In operation, the first clock signal is fed downstream (via the facility having the delay), thereby triggering the second clock signal. The two clock signals are then detected and the difference in the two clock readings computed, thereby forming .DELTA..sub.n. The process is then repeated for successive first and second clock signals, thereby forming .DELTA..sub.n+1. The absolute value of .DELTA..sub.n -.DELTA..sub.n+a is then compared with a predetermined value to determine whether the facility time delay has changed. This method is particularly useful in simulcast broadcast systems.

REFERENCES:
patent: 4001690 (1977-01-01), Mack et al.
patent: 4255814 (1981-03-01), Osborn
patent: 4494211 (1985-01-01), Schwartz
patent: 4651330 (1987-03-01), Ballance
patent: 4696051 (1987-09-01), Breeden
patent: 4718109 (1988-01-01), Breeden et al.
patent: 4800560 (1989-01-01), Aoki et al.
patent: 4807259 (1989-02-01), Yamanaka et al.

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