Delay element that has a variable wide-range delay capability

Details Delay element that has a variable wide-range delay capability Delay element that has a variable wide-range delay capability

2000-04-06

2001-07-31

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S274000, C327S278000

Reexamination Certificate

active

06268753

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of signal delay systems, and more particularly, to digital signal variable delay systems.
2. Description of the Related Art
Two commonly used methods of variable delay systems are MOS-based and ECL-based delay systems.
FIG. 1
a
shows a MOS-based method for the delay of digital signals. The inverter stages, comprised of MOSFET pairs
10
and
12
,
14
and
16
,
18
and
20
, and
22
and
24
, are used to delay the input signal (Vin)
26
. Multiple delay elements
30
,
32
,
34
,
36
denoted as D
o
-D
x
are cascaded together to obtain the desired delay from input signal Vin
26
to output signal (Vout)
28
. Due to the variable resistance characteristics of MOSFET devices, the delay through each inverter stage can be varied by changing the conductance of each MOSFET pair,
10
and
12
,
14
and
16
,
18
and
20
, and
22
and
24
, conductance being inversely proportional to the resistance. This is achieved by varying the gate-to-source voltage, Vgs, of each MOSFET device with the control voltage (Vc)
38
. As voltage
38
is increased, the drain-to-source conductance, Gds, through each inverter stage,
10
and
12
,
14
and
16
,
18
and
20
, and
22
and
24
, is also increased, thus reducing the delay through each delay element
30
,
32
,
34
,
36
. Similarly, decreasing voltage
38
increases the delay time by decreasing Gds.
Typically, the propagation delay of CMOS devices can vary widely due to process, voltage, and temperature variations. Process variations in the width and thickness of the diffusion and oxide layers can produce variations in device performance. In addition, the drain current of CMOS devices decreases as the temperature increases, which causes an increase in propagation delay. Moreover, voltage variations also affect the delay characteristics. All of these variations must be compensated to obtain predictable and tightly controlled delays in MOS-based delay circuits such as the example given in
FIG. 1
a
. This requires the means to calibrate or tune the delay circuit to obtain a desired delay characteristic over all conditions of process, voltage, and temperature.
One such method for calibration and tuning used in prior art applications is shown in
FIG. 1
b
. The inverter-based delay line of
FIG. 1
a
is shown as a block diagram
48
in
FIG. 1
b
, configured with a block diagram of a Phase-Locked Loop (PLL)
40
. The PLL shown is comprised of a voltage-controlled ring oscillator (VCO)
42
, a frequency divider
44
, and a phase detector
46
. The VCO
42
is a separate delay line with a feedback path from the delay line's output to its input. The VCO
42
delay line is identical to the delay line
48
. The oscillation frequency of the VCO
42
is determined by the number of delay elements
30
,
32
,
34
,
36
in the VCO
42
, and the propagation delay through each element which is controlled by control voltage
54
. Since the delay line
48
is identical to the VCO delay line
42
, a known delay can be specified by setting the frequency of VCO
42
to a known value. The output of VCO
42
is divided down by divider
44
and output at
56
(Fout/N). The phase detector
46
compares the phase and frequency of Fref
50
with the frequency out
56
(Fout/N) of the divider
44
and adjusts control voltage Vc
54
accordingly. If frequency Fref
50
is less than the frequency
56
(Fout/N), then the phase detector
46
decreases Vc
54
. The amount of delay from Vin
26
to Vout
28
can be accurately controlled by the action of the PLL
40
, which adjusts the matching VCO
42
to lock to the input reference frequency, Fref
50
. Various delays can thus be achieved by proper selection of the Fref
50
input frequency and the 1/N frequency divider
44
. Accordingly, use of a PLL
40
allows tightly controlled delays that are not sensitive to process, voltage, and temperature.
Even though inverter-based delay elements, such as those shown in
FIG. 1
a
, have been widely used for delay generation in MOS integrated circuit (IC) designs, their use has generally been reserved for non critical delays when tightly controlled delays, that might require a compensation means to insure delay precision, are not required. The approach of
FIG. 1
b
is not desirable for many applications due to the requirement of the PLL
40
, which will consume additional area and power. Furthermore, the additional clock switching noise contributed by the reference voltage input
50
and the PLL
40
logic circuits can adversely affect the performance of the other circuit sections on the IC, such as the delay elements, and thus cannot be ignored as well.
FIG. 2
shows an ECL-based method for the delay of digital signals. In its simplest form, an ECL-based delay element can be constructed as shown in
FIG. 2
a
. Here, differential input signals
60
and
62
are delayed by the emitter-coupled differential pair comprised of transistors
66
and
68
. The collector voltages of the differential pair are buffered by emitter followers
70
and
72
for interfacing of the output signals
74
and
76
to subsequent delay stages. The delay of this delay element can be varied by changing the voltage at the base of transistor
78
, the Vx input
64
. As the Vx voltage
64
increases, the current through resistors
80
and
82
also increases, thus decreasing the delay through the delay cell. This type of approach suffers from the same limitations as the MOS-based delay elements of
FIG. 1
since the delay of the delay elements in
FIG. 2
a
is highly dependent upon process, voltage, and temperature variations.
Improvements to the circuit of
FIG. 2
a
can be made if MOSFET devices are used, such as would be true on a BICMOS integrated circuit. In
FIG. 2
b
PFETs
84
and
86
have been added in parallel to resistors
80
and
82
to provide another means for controlling the delay through the delay element. As the Vgs voltage
88
increases in the negative direction, the Gds of the PFETs
84
and
86
also increases, reducing the resistance at the collectors of
66
and
68
. Addition of the capacitors
90
and
92
serves to extend the range of the delay as may be desired by the user, due to the capacitors' charging/discharging time. Capacitors
90
and
92
also serve to swamp the parasitic capacitances, which may be present at the transistor collectors, thus reducing the effect of the device parasitics on the delay generation As in
FIG. 2
a
, the delay through the delay element can be varied by changing the control voltage
64
. At the same time, however, the Vgs voltage
88
can also be varied to maintain a constant voltage swing at the collectors of transistors
66
and
68
by causing a set resistance across resistors
80
and
82
that is constant regardless of temperature and voltage. As Vgs
88
increases in the negative direction, the resistance across resistor
80
approaches that of a short circuit. As Vgs
88
decreases, the resistance across resistor
80
approaches that of an open circuit. Thus the delay through the element can be controlled in a more precise manner than in the previous design. If the voltage at the collectors of transistors
66
and
68
is held constant, then the maximum delay is determined by resistors
80
and
82
. The minimum delay will be determined by the minimum parallel resistance of the resistors and the PFET devices. Even though the PFET devices in
FIG. 2
b
, which allow the user to vary the resistance, have been used in delay element applications, further improvements can be made to enhance their ability to control the delay of such designs.
Accordingly, there is a need for a wide-range variable delay system that can delay multiple signals in a precise manner regardless of process, voltage, and temperature variations.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a wide-range variable delay system that substantially obviates one or more of the problems arising from the limitations and disadvantages of the

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