Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-01-22
2002-06-04
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S407000, C327S160000
Reexamination Certificate
active
06400197
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89101270, filed Jan. 26, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a signal delay device and a method of calibrating the delay period. More particularly, the present invention relates to a signal delay device having an internal delay lock loop for calibrating the delay interval.
2. Description of Related Art
Due to the rapid progress in semiconductor technologies, computational capability of a computer increases at a tremendous pace. At present, most computers are constructed using digital circuits. Synchronization among various internal devices is achieved using one or more reference clock signals such that various devices cooperate each other. In earlier computer system, data can be easily transferred among internal devices because the operating speed is low.
FIG. 1
illustrates a conventional timing diagram of data transmission using a clock. In
FIG. 1
, signal DAT represents transmission data and signal CLK represents the waveform of a system clock. Since the data signal DAT varies according to the clock signal CLK, the receiving terminal of a device is able to receive the data signal correctly. However, this method is only suitable for the transmission of data in earlier operating system. As the operating frequency of a system increases, precision of data transmission is difficult to maintain in the same way so as to lead to many possible system problems.
FIG. 2
illustrates a circuit block diagram of a conventional data transmission system using a clock signal. As shown in
FIG. 2
, a transmission device
210
transmits data signals DAT to a receiving device
220
through a transmission line
230
. During transmission, signal is delayed due to the buffer
214
inside the transmission device
210
, the buffer
224
inside the receiving device
220
and the transmission line
230
(flight time). In addition, the flip-flop
212
inside the transmission device
210
and the flip-flop
222
inside the receiving device
220
both use the clock signal CLK to latch-up the data. The clock signal CLK propagating through the transmission line
240
results in clock skew due to the delay in the circuit. In an actual digital system, there can be a total signal delay of 2~3 ns (nano-second) from the transmitting terminal to the receiving terminal. Due to the above consideration, data holding time on data line must be extended for accurate transmission of data through the circuit. Inconsequence, it is difficult to raise clock frequency and data transmission rate.
To reduce clock delay and data loss problem during data transmission, data strobe signals are introduced.
FIG. 3A
illustrates a circuit block diagram of a conventional data transmission system with data strobe.
FIG. 3B
illustrates a timing diagram showing data strobe and data line waveform. As shown in
FIG. 3A
, the flip-flop
316
inside the transmission device
310
converts a clock signal CLK into a data strobe signal DS. Data signal DAT is sent accompanied by the data strobe signals DS. The flip-flop
322
inside the receiving device
320
receives data according to the data strobe signal DS. Hence, delay T
buffer
for the buffers and flight time on the transmission line T
flight
are eliminated. Furthermore, both the rising edge and the falling edge of the data strobe signal DS can be used for data transmission. In other words, the system is capable of operation in a double data rate (DDR) mode, for example, in DDR SDRAM (synchronous dynamic random access memory). If skew of the data strobe signal DS between the transmission terminal and the receiving terminal can be disregarded, transmission speed is limited by the setup and hold time of the flip-flop
322
inside the receiving device
320
only. In general, the setup time is about 0.5 ns and hold time is about 0.5 ns.
In real applications, data signal DAT and data strobe signal DS are generated and transmitted from the transmission terminal synchronously. In other words, data signal DAT and data strobe signal DS are transmitted from the transmitting terminal at the rising or falling edge of a clock signal. By having the same delay trace, delay time T
buffer
of the buffers and delay time T
flight
of the transmission line are balanced, and skew between the data signal DAT and data strobe signal DS is minimized. Timing sequence of the signal transmission is shown in FIG.
3
B. However, since data access is carried out at the rising edge or falling edge of a data strobe signal DS, the data strobe signal DS must be delayed for a period of time at the receiving device
320
to ensure data accuracy.
FIG. 4A
illustrates a block diagram showing the addition of a data delay element at the receiving terminal of a conventional data transmission system.
FIG. 4B
illustrates a timing diagram of data strobe signal, data signal and delayed data strobe signal. As shown in
FIGS. 4A and 4B
, the rising edge and the falling edge of the data strobe signal DS′ that trigger the flip-flop
422
are within the stable portion of the data signal DAT. Hence, the flip-flop
422
is able to latch-up the data precisely.
There are a few types of delay elements. For example, a winding circuit line on a printed circuit board can be used to increase transmission time. Alternatively, passive devices inside an integrated circuit can be used as a delay element. However, both types of delay elements are not so suitable for forming a high efficiency circuit. Winding a long circuit line on a printed circuit board will occupy a large area, and hence will decrease the level of integration. Due to circuit fabrication, the same passive delay elements inside an integrated circuit share different delay time. The maximum delay time in a delay element can be twice the minimum delay time. For example, if the intended delay time of a delay element is Ins, delay time of the actual delay element may vary from 0.67 ns to 2 ns.
The design of delay element is rather difficult because too much or too little delay for the data strobe signal will lead to the interception of inaccurate data. In fact, accuracy of received data depends on whether the amount of delay (D
ds
—
da
) between the data strobe signal DS and the data signal DAT is appropriate. In other words, accuracy depends on whether the rising or falling edge of the data strobe signal DS resides within a stable portion for reading data signal DAT.
Factors that affect the amount of delay D
ds
—
da
between data strobe signal DS and data signal DAT includes: 1. Skew between data strobe signal DS and data signal DAT from the transmission terminal to the receiving terminal (&rgr;s); 2.Delay caused by the delay element (sd). Hence, the amount of total delay D
ds
—
da
between data strobe signal DS and data signal DAT is &rgr;s+sd. Factors that affect signal skew &rgr;s includes: various differences among output buffers, layout on a printed circuit board, threshold voltage of output buffers, setup time and hold time for flip-flops and so on. On the other hand, factors that affect the delay time of a delay element includes: design of the delay element, temperature, humidity, voltage, CPU operating frequency, electromagnetic interference and so on. For example, due to the dynamic influence by various factors, there is a possible delay of between 0.5~1.8 ns for a 66 Mhz system. Furthermore, the amount of delay is different for different operating frequencies such as 66 Mhz, 75 Mhz, 83 Mhz, 100 Mhz, 133 Mhz and higher. In general, as the operating frequency is increased, clock signal cycle is shortened and tolerable error range is reduced. Whenever the data strobe signal DS is too long or too short, the receiving terminal latches inaccurate data such that the system can not operate normally Moreover, even if an accurate delay value is estimated, the delay value may still vary according to changes in other factors such as temperature, voltage, frequency or electromagnetic interference. Hence, &rg
Lai Jiin
Lin Hsin-Chieh
Liu Kuo-Ping
J.C. Patents
Nuton My-Trang
VIA Technologies Inc.
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