Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-01-18
2001-10-16
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S143000, C324S142000, C324S622000, C702S089000
Reexamination Certificate
active
06304202
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to analog-to-digital converters and more particularly to phase equalization in a dual-channel analog-to-digital converter used in a power meter.
2. Description of the Related Art
Energy calculations for electric power loads are made by power meters of all kinds. Until recently, electromechanical power meters were exclusively employed in millions of homes and businesses worldwide to monitor the amount of power consumption by a user at a particular location. Such monitoring allows the electricity/power entities to monitor the power (energy) usage of the user for proper billing, load monitoring, servicing, etc. In electromechanical power meters, a series of electrical components as well as mechanical disks, gears, indicators, and dials are used to convert voltage and current into energy. In addition to low accuracy, these electromechanical power meters also require periodic manual calibration and check-ups by field service technicians to ensure that they are operating properly. Digital meters have recently begun to replace electromechanical meters in monitoring power consumption for homes and businesses. In general, because they rely on digital rather than electromechanical components, digital meters are more accurate and reliable than their counterpart electromechanical meters. Additionally, through networking, digital meters allow calibration and monitoring check-ups to be performed from a remote location such as a central office, thereby greatly reducing the on-site visits by field service technicians. Finally, due to deregulation of the electricity market in the United States and Europe, a broader range of information on consumer power use is needed by competing power suppliers for customizing the billing and servicing plan for each consumer. Due to these advantages, in the near future, digital meters will likely replace all of the 60 million electromechanical power meters that are in use today in industrial and residential applications. In general, electronic (digital) power meters use sensors such as transformers, for example, to measure the analog current and voltage from the power lines. These measurements are converted into digital words using analog-to-digital converters (ADCs). A power value P is then computed using the converted digital current words and the converted digital voltage words, according to the equation P=V*I wherein V represents voltage and I represents current. However, the measurement process and conversion process may introduce delays into signals carrying the digital voltage words and digital current words, which can cause the signals to be out of phase relative to each other. One technique to equalize the phase change involves compensating the sensors. This, however, may be expensive because it requires making physical adjustments to passive devices. Another technique to equalize the phase change involves scaling the power output value by a predetermined scaling factor after it has been computed. This technique is based upon the power equation P=I*V*cos &phgr; that relates voltage V, current I, and the phase error &phgr; between I and V. According to this technique, the power value P is divided by the factor cos &phgr; to compensate for the phase error between I and V. This requires prior knowledge of the phase error &phgr;. However, the error angle &phgr; is a function of frequency which may drift over time, thereby making the scaling factor cos &phgr; variable. As such, the power value computed using a fixed scaling factor cos &phgr; may thus be inaccurate. In addition, an actual phase angle &phgr;
A
between the current and voltage may exist as the load becomes less resistive. This also will produce an error in the computed power value.
The energy consumed by a particular electric power load can be calculated according to the following formulas:
E
=
∫
ti
tf
P
(
t
)
ⅆ
t
and
E
=
∫
ti
tf
I
(
t
)
V
(
t
)
ⅆ
t
The energy calculation can be carried out in a sampled data domain, permitting digital multiplication. The measurement system including sensors and analog-to-digital converters (ADCs), contributes different delays to the voltage and current channels. The error results in a difference in calculated watt-hours between watt-hours calculated with and without delays. In the past, the sample clock for the ADCs has been shifted, making necessary the design of a complex clock generator, not only for the ADCs but for any filters in the signal paths. For example, see Coln, et al., U.S. Pat. No. 5,017,860.
SUMMARY OF THE INVENTION
According to the present invention, filter correction in a dual-channel analog-to-digital converter (ADC) is accomplished by delaying conversion results in fixed length registers. According to one embodiment of the present invention, a dual-channel ADC includes first and second delta-sigma modulators and digital filters, subject to multiple sampling rates suitable for optimizing coarse and fine adjustments of delay. Further according to the present invention, an energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques. In particular according to the present invention, the digital data subject to filter processing is delayed by predetermined amounts. According to the present invention there is further no need to shift the sample clock of the ADCs, which would require a complex clock generator not only for the ADC components but for any filters in the signal paths of interest. Further, according to the present invention, a differential delay is compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADCs. Thus according to the present invention, the analog signals are left alone and not adjusted. Instead, the data which comes out of the analog circuitry is treated as normal, and delay circuitry is connected between the filter circuitry according to the present embodiment.
REFERENCES:
patent: 4463311 (1984-07-01), Kobayashi
patent: 5124656 (1992-06-01), Yassa et al.
patent: 5485393 (1996-01-01), Bradford
patent: 5764523 (1998-06-01), Yoshinaga et al.
patent: 5963074 (1999-10-01), Arkin
patent: 6166573 (2000-12-01), Moore et al.
King Eric T.
Pastorello Douglas F.
Cirrus Logic Inc.
Lin Steven
Protigal Stanley N.
Williams Howard L.
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