Excavating
Patent
1997-04-25
1998-08-18
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
057967490
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a delay correction circuit for a semiconductor device tester to correct the timings of signals applied to semiconductor devices under test and to establish a phase relationship between the signals when a plurality of test stations for are provided to test the semiconductor devices under test simultaneously by the semiconductor device tester.
BACKGROUND ART
Generally, a plurality of test stations are used to test and process many semiconductor devices to be tested efficiently in a semiconductor tester. The devices to be tested are electrically connected to the test stations through IC sockets, and the device test proceeds simultaneously for each semiconductor device under test. Waveforms of test signals for each device under test must be applied in the same condition. Hence, the semiconductor tester is so composed as to include a timing correction circuit for each test station to correct the differences between the timings of the test signals and synchronizes the phase of the test signals at each device terminal to be tested.
FIG. 3 shows an example of a delay correction circuit in a conventional semiconductor tester. A timing correction part 10 is provided for each pin of the device to be tested as designated by #1, #2, . . . #n. An output signal of a corresponding pin of the device is taken out as an output signal 61 for a test station 1 and an output signal 62 of another device is taken out for a test station 2. The wave form to be provided to the test station 1 (21) and to the test station 2 (22) is generated by a waveform controller 11. A signal for determining whether this waveform should be provided through a driver terminal to the device is generated by a waveform output controller 12. Waveform output control signals 51 and 52 for corresponding test stations are adjusted in the timing at a flip-flop 13 by a timing clock 50, and are taken out as signals 53 and 54. A logical AND is established between a signal from the waveform controller 11 and the signal 53 from the flip-flop 13 by an AND gate 14 to produce a signal for the test station 1. Similarly, a logical AND is established between the signal from the waveform controller 11 and the signal 54 from the flip-flop 13 by an AND gate 15 to produce a signal for the test station 2. The flip-flop noted above may be a edge type flip-flop or a latch type flip-flop.
In general, the waveforms generated by the waveform controller 11 differ their phases with respect to each pin of the device under test. This is because the phase differences are caused by the complexity of waveforms provided to the device to be tested, which in turn necessitates the waveform controller 11 to have a large number of gate circuits, thereby vary the accumulated propagation delay times of the gate circuits for the corresponding pins of the device. Hence, variable delay elements (16, 17) are provided at the timing correction part 10 so as to correct this phase differences between the pins. In addition, the small differences of the delay times occur between the test station 1 and the test station 2. This is mainly caused by the difference in the cable lengths used in the test stations. Hence, the variable delay elements are provided at each test station as well. A variable delay element 16 for the test station 1 covers both of the two kinds of delay times noted above. A variable delay element 17 for the test station 2 covers both of the other two kinds of delay times noted above.
Assuming an adjustable range stemming from the delay time difference for the test station 1 as A1, an adjustable range stemming from the delay time difference of the test station 2 as A2, and an adjustable range stemming from the delay time difference of the waveform controller as B. Then an adjustable range S1 to be covered by the variable delay element 16 for the test station 1 is represented as; for the test station 2 is represented as; times in the timing correction part common to all the test stations and in the timing correction part independent for each te
REFERENCES:
patent: 5544105 (1996-08-01), Hirose et al.
patent: 5629900 (1997-05-01), Hirose et al.
Advantest Corp.
Canney Vincent P.
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