Delay control circuit

Details Delay control circuit Delay control circuit

1997-09-24

1999-05-04

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, 327276, 327141, 327149, 327151, 327153, 327150, 327277, 327371, 327373, H03K 5159

Patent

active

059007540

ABSTRACT:
A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

REFERENCES:
patent: 3479598 (1969-11-01), Weller
patent: 4813005 (1989-03-01), Redig et al.

Affiliated with

Also associated with

Rating

Delay control circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay control circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay control circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1871861