Delay compensation technique for buffers

Details Delay compensation technique for buffers Delay compensation technique for buffers

1992-09-17

1994-04-05

Wambach, Margaret R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072966, 3072968, 307594, 307597, 307603, 307605, H03K 301, G06G 710

Patent

active

053008375

ABSTRACT:
An integrated circuit has a signal path including a first circuit that introduces a propagation delay that decreases with circuit conditions and process speed in series with a second circuit that introduces a propagation delay that increases with circuit conditions and process speed. The circuit conditions and process speed are sensed and the duration of the propagation delay of the second circuit varied such that the total propagation delay remains within a predetermined range over circuit condition and process speed variations. In another embodiment of the invention, a current source develops a bias current to control the duration of the propagation delay of the second circuit. In yet another embodiment of the invention the current source is a current mirror.

REFERENCES:
patent: 4791326 (1988-12-01), Vajdic et al.
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5164621 (1992-11-01), Miyamoto
patent: 5179297 (1993-01-01), Hsueh et al.
Johnson et al., "A Variable Delay Line Phase Locked Loop for CPU-Coprocessor Synchronization," 1988 IEEE International Solid-State Circuits Conference, Feb. 18, 1988, pp. 142-143.

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