Delay compensation circuit

Details Delay compensation circuit Delay compensation circuit

2001-11-15

2004-11-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S265000, C327S279000, C327S284000, C327S378000, C327S062000

Reexamination Certificate

active

06819157

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to synchronous circuit design, and more particularly, to a circuit for measuring and compensating for variations in the process, voltage and temperature (PVT) conditions of an integrated circuit.
DESCRIPTION OF THE RELATED ART
In digital circuits, synchronous logic elements operate by accepting and locking into a data signal during a transition of a clock signal. Such logic elements include D flip-flops, latch circuits, linear feedback shift registers (LFSRs), and counters. In order for a synchronous logic element to lock into a data signal, the signal must remain stable for some time prior to the clock edge, i.e., during a setup time. Also, the data signal usually must remain stable for some time after the clock edge, i.e., during a hold time, to be locked in by the synchronous logic element. If the data signal is not stable for both the setup time and the hold time of a synchronous logic element, the data signal may or may not be captured by the logic element.
FIG. 1A
illustrates the operation of a synchronous logic element, specifically a D flip-flop DFF. In this example, the input data signal A is also used as the clock signal. Typically, the data signal and the clock signal are not shared, but instead are distinct signals. They are shown as sharing the same signal in
FIGS. 1A and 1B
to simplify the description of the related art. All descriptions herein apply to the case where the clock and data signals are distinct.
As shown in the timing diagrams of
FIG. 1A
, signal A is applied at the D input and clock input CK of the D flip-flop DFF. Therefore, the required setup time T
su
of the flip-flop DFF cannot be satisfied, and the Q output is indeterminate. This situation is shown in the timing diagram of FIG.
1
A. However, such violations of setup time are not limited to instances where the input data signal is used to clock itself in a synchronous logic element.
For instance, clock skew (i.e., minor variations in the time at which clock signals arrive at their destinations in a chip) may cause the clock signal to arrive earlier than expected. Therefore, clock skew may cause a data signal to violate the setup time. Clock skew can be caused by, among other things, the process, voltage, and temperature (PVT) conditions of the synchronous logic element.
One way to prevent setup time violations is to add a delay element to the path of the clock signal.
FIG. 1B
shows a delay element added to the clock path of the D flip-flop DFF in FIG.
1
A. As shown in the timing diagram of
FIG. 1B
, the delay element delays the signal A applied to the CK input by a time T
d
, thereby shifting the clock edge such that the data signal is stable during the setup time T
su
.
However, the delay time T
d
may vary according to the PVT conditions of the delay element. For example, if the temperature varies between from about −40°C. to 125° C., the supply voltage varies by +/−15%, and/or the process conditions of the delay element varies between worst case fast and worst case slow, the delay time T
d
may vary from below 50% to over 100% of the designated delay time T
d
. Such changes in delay time T
d
may result in a violation of the setup time or the hold time of the D flip-flop DFF, or other types of synchronous logic elements.
One solution to this problem has been to use a type of variable delay element consisting of several small delay cells, where each small delay cell has a relatively short delay time T
s
. The number of small delay cells within the variable delay element that are effectively used to delay the clock signal can be changed, based on PVT conditions. Accordingly, the delay time T
d
of the variable delay element (the sum total of delay times T
s
of the effective small delay cells) of the effective can be kept constant, despite variances in PVT conditions. The tapped delay circuit
10
, illustrated in
FIG. 2
, is an example of such a variable delay circuit.
As shown in
FIG. 2
, a tapped delay circuit
10
is comprised of a group of tapped small delay cells SD
1
, . . . , SD
8
, which are connected in series. The DELC1V15 delay component is an exemplary type of small delay cell SDn (n being within the range of 1 to 8 in
FIG. 2
) that can be used in tapped delay circuit
10
. The DELC1V15 component has an expected delay time in worst case fast conditions of about 0.4 nanoseconds (ns), and an expected delay time during worst case slow conditions of about 1.0 ns. However, for the tapped delay circuit
10
and other subsequently described circuits, any component having a known delay time T
s
may be used instead of the DELC1V15 component. The desired resolution and the frequency of the input clock, CLK, generally determine the selection of the delay component.
As discussed above, each small delay cell SDn in
FIG. 2
has a relatively short time delay time T
s
. An input signal IN is input to the first small delay cell, and the delayed signal propagates from small delay cell SD
1
to the next small delay cell SD
2
to the next small delay cell SD
3
, etc., until it propagates to the last small delay cell SD
8
. Therefore, the signal at tap
1
will be delayed by T
s
, the signal at tap
2
will be delayed by 2*T
s
, and so forth. Multiplexor MUXA selects and outputs the tap signal based corresponding to a series number received via control signal CTL.
FIG. 3
illustrates a variable delay control circuit
100
, in which the delay time T
d
of tapped delay circuit
10
of
FIG. 2
is controlled by shift register array
30
and phase detector
40
, through adjustment of the series number. The number of small delay cells SDn in tapped delay circuit
10
is based on the desired resolution of variable delay control circuit
100
.
The shift register array
30
contains the series number, which comprises a number of bits that corresponds to the number of small delay cells SDn. If the tapped delay circuit
10
has eight small delay cells SDn, as illustrated in
FIG. 2
, the shift register array
30
will hold a series number comprising eight digits. Each digit corresponds to a specific small delay cell tap. One of the digits contains a “1” bit while all of the other digits contain “0” bits. The digit containing the “1” bit corresponds to the tap whose signal is selected and output by multiplexor MUX A.
The variable delay control circuit
100
operates as follows. First, an input clock signal CLK is input to the first tapped delay circuit
10
of the tapped delay circuit
10
. The tapped delay circuit
10
outputs a clock signal P_CK delayed according to delay time T
d
, which is determined by the series number in shift register array
30
. Both the delayed clock signal P_CK and the input clock signal CLK are sent to phase detector
40
, which detects a phase difference between the input clock CLK and the delayed clock signal P_CK.
Based on a detected phase difference, phase detector
40
will generate either a right shift signal CSR or a left shift signal CSL, if necessary, which shifts the “1” bit of the series number in the shift register array
30
to either the left or right. As a result of the modified series number, the multiplexor MUX A of the tapped delay circuit
10
will select and output a different tap signal.
The variable delay control circuit
100
of
FIG. 3
can be considered a type of delay-locked loop (DLL), because it synchronizes or aligns the delayed clock signal PCK
13
CK with the input clock signal CLK.
FIG. 4
illustrates a timing diagram including reference signals P_d
0
and P_d
1
of phase detector
40
, which are generated based on clock signal CLK. Specifically, the phases of P_d
0
and P_d
1
define the boundaries of an optimally delayed clock signal. In other words, if the time delay T
d
of the tapped delay circuit
10
is within circuit design requirements (e.g., meet required setup and hold times), the phase of P_CK will fall between the phases of P_d
0
and P_d
1
. Therefore, phase detector
40
compares the phase of P_CK signal to P_d
0
and P_d
1
to determine wh

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