Delay compensated signal propagation

Details Delay compensated signal propagation Delay compensated signal propagation

1994-11-10

1995-12-12

Hsu, Alpus

Multiplex communications

Wide area network

Packet switching

370108, 327153, 327271, 375371, 395550, H04J 306

Patent

active

054756901

ABSTRACT:
In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.

REFERENCES:
patent: 4055851 (1977-10-01), Jenkins et al.
patent: 4151593 (1979-04-01), Jenkins et al.
patent: 4897783 (1990-01-01), Nay
patent: 5229668 (1993-07-01), Hughes et al.
patent: 5325508 (1994-06-01), Parks et al.

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