Delay-compensated fractional-N frequency synthesizer

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S156000, C331S016000, C331S017000

Reexamination Certificate

active

06943600

ABSTRACT:
A Phase-Locked Loop is provided that includes a main loop, a calibration loop, and Control Logic. The main loop comprises, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Voltage Controlled Oscillator and a Frequency Divider. The calibration loop is coupled to the Phase Frequency Detector and comprises a Calibration Charge Pump and a Calibration Loop Filter. The Control Logic controls the Frequency Divider and receives a control input signal. A Reference Frequency Signal is coupled to the Phase Frequency Detector and the Control Logic, and a calibration signal is coupled to the calibration loop. Additionally, the main loop further comprises a delay generator controlled by the Control Logic and arranged to receive correction signals from the calibration loop and to send an output signal to the Phase Frequency Detector.

REFERENCES:
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patent: 6064272 (2000-05-01), Rhee
patent: 6094082 (2000-07-01), Gaudet
patent: 6359950 (2002-03-01), Gossmann et al.
patent: 6501336 (2002-12-01), Kim et al.
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patent: 6882831 (2005-04-01), Shi et al.
patent: 2001/0033201 (2001-10-01), Canard et al.
patent: 56169927 (1981-12-01), None
patent: WO 86/07219 (1986-12-01), None
European Search Report dated May 14, 2003 for European Application No. 02-447268.0.

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