Delay clock pulse-width adjusting circuit for intermediate...

Details Delay clock pulse-width adjusting circuit for intermediate... Delay clock pulse-width adjusting circuit for intermediate...

2002-10-24

2004-10-05

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S170000

Reexamination Certificate

active

06801068

ABSTRACT:

FIELD OF THE TECHNOLOGY
The present invention relates generally to a delay clock pulse-width adjusting circuit, and more particularly to a delay clock pulse-width adjusting circuit which is consisted of a delay comparator and a converting circuit, which converts the duty-ratio of a clock signal to a DC level.
BACKGROUND OF THE INVENTION
In a modern signal processing system, a clock signal is indispensable. Along with the rapid development of some technical fields such as the communication, the requirement of a clock signal is getting higher. The main requirements are shown in the followings:
(1) The high frequency accuracy of a clock signal, which is solved by using a crystal oscillator or atomic clock;
(2) The long time stability of a clock signal, it is required that for one year or even longer there is only one second error or lower than one second error of a clock signal; this is solved by the clock source stability;
(3) The duty-ratio stability of a clock signal, the larger duty-ratio deviation of a clock signal can cause a larger error rate in a communication system. In an A/D converter, a sample rate in a sample/hold circuit is defined at design stage. If the duty-ratio of a clock signal changes, charging time for some capacitors will be decreased, so converting accuracy will be lower than the requirement.
FIG. 1
is a schematic diagram of a present clock generator. As shown in
FIG. 1
, a duty-ratio change of the clock signal mainly comes from two aspects: a system error and a random error. The system error includes a voltage amplitude change of the crystal oscillator output, a harmonics produced by loads of the clock, a change of the DC trigger level and the temperature drift etc. The random error mainly comes from the followings: a DC component deviation of the sine wave output of a crystal oscillator, a random deviation in the comparator input grade and a deviation of the DC triggering level etc.
To simplify the analysis process, all the errors are converted to a sine output of the crystal oscillator. Also, suppose a signal deviation is smaller; i.e. when analyzing error influence on a duty-ratio, according to the sine wave equation, change of a trigger time is:
&Dgr;
V=V
sin(2
nf×&Dgr;t
)  (1)
Wherein V is amplitude of the sine wave, f is a frequency and &Dgr;V is a DC component change of the sine wave. Suppose V>>&Dgr;V, according to the approximate equation of a sine function, from formula (1) the change of a trigger time can be approximately expressed by:
&Dgr;
t=&Dgr;VIV×
2
nf
  (2)
Since trigger time is same for leading triggering edge and falling triggering edge, so according to formula (2) change of the duty-ratio can be expressed as:
 
&Dgr;D=&Dgr;VInV
  (3)
From formula (3), the signal, shown in
FIG. 2
, can be obtained.
It is seen from
FIG. 2
that for the ideal clock signal if duty=t
2
/(tl+t
2
), then the signal DC level is consistent with the DC component of the sine wave. For the real clock signal, the DC trigger level is not consistent with the DC component of the sine wave, as shown by real line and dot line in
FIG. 2
respectively. In
FIG. 2
, DC component change of the sine wave outputted by the crystal oscillator is a negative polarity, but in real, changing polarity can be positive or negative.
SUMMARY OF THE INVENTION
The purpose of the invention is to provide a delay clock pulse-width adjusting circuit which can be used in a clock signal circuit for intermediate frequency or high frequency. With this adjusting circuit, the duty-ratio of a clock signal is no larger abrupt change, so burden of the digital signal processing is decreased. The adjusting circuit also is suitable for submicron integrated circuit technology, so it will decrease influence of the random error during chips manufacturing process. Consequently, the adjusting circuit makes chips of digital-analog hybrid integrated circuit satisfy the requirement: high traffic, low error rate and high stability of the clock signal duty-ratio.
For the purpose mentioned above, the invention first provides a delay clock pulse-width adjusting circuit for intermediate frequency or high frequency with a delay comparator and a power supply. It is important that the adjusting circuit also includes:
One input terminal of the delay comparator inputs a sine wave signal which compares with a voltage inputted from another input terminal of the delay comparator, and the output is a defined duty-ratio clock signal; and
A converting circuit converts a clock signal duty-ratio to a DC level. Input terminal of the converting circuit is connected to output terminal of the said delay comparator, and output of the converting circuit is a DC level which is converted from the said clock signal. Again, output terminal of the converting circuit is connected to another input terminal of the said delay comparator.
Said converting circuit is mainly consisted of a Pulse-Width Modulation (PWM) filter module, which converts a clock signal to a DC level.
Said converting circuit is mainly consisted of a pulse-width modulator (PWM) filter module and a low pass filter circuit. The PWM filter module converts a clock signal to a DC level. The low pass filter circuit filters the DC level outputted from the PWM filter module then outputs to the delay comparator as an input.
Said low pass filter is a transconductance operational amplifier.
Said PWM filter comprises an inverter, whose input is a clock signal and output is an inverted clock signal; first switch, which is controlled by the inverted clock signal; second switch, which is controlled by the clock signal; first current source, which is connected to the supply with one end and to the first switch with another end; second current source, which is connected to the ground with one end and is connected to a node A with another end; third current source, which is connected to the ground with one end and to the second switch with another end; first current mirror, which is connected to the second switch with one end and is connected to the supply with another end; second current mirror, which is connected to the supply with one end and to the output with another end, and a current to voltage converter, which is connected to the ground with one end and to the output with another end.
Said first switch is an OR gate consisted of a pair of PMOS transistors, and said second switch is an OR gate consisted of a pair of NMOS transistors. Said a current mirror is consisted of two MOS transistors with the connections as follow: the drain and gate of one MOS transistor is connected with the gate of another MOS transistor, the sources of the two MOS transistors are connected with the supply, and the drain of another MOS transistor is the output. Said current to voltage converter is a capacitor.
Said converting circuit at least includes:
A detection circuit is used to detect whether the input clock signal, which is the output of said delay comparator, exists a floating signal and to output a voltage difference according to the floating signal; and
A correction circuit is used to correct the threshold voltage input of said delay comparator according to the voltage difference output of the detection circuit.
Said detection circuit has an inverter, which inverts an input clock signal to output an inverted clock signal; a current switch, which is controlled by the clock signal and inverted clock signal; first current mirror circuit, which is connected with one input of the current switch and charges the capacitor of the correction circuit when the clock signal is a high level; second current mirror circuit, which is connected to another input of the current switch; and third current mirror circuit, which is connected with second current mirror circuit and discharges the capacitor of the correction circuit when the clock signal is a low level.
Said detection circuit also has a current source circuit used to provide a bias current to the current switch.
There is another detection circuit. The detection circ

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