Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2007-01-23
2007-01-23
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S264000, C327S285000
Reexamination Certificate
active
11063070
ABSTRACT:
One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.
REFERENCES:
patent: 4805195 (1989-02-01), Keegan
patent: 5959487 (1999-09-01), Kawamura
patent: 6259330 (2001-07-01), Arai
patent: 6269060 (2001-07-01), Harvey et al.
patent: 6414527 (2002-07-01), Seno
patent: 6509788 (2003-01-01), Naffziger
patent: 6518812 (2003-02-01), Sikkink et al.
patent: 6535735 (2003-03-01), Underbrink
patent: 6573776 (2003-06-01), Miyamoto
patent: 6667651 (2003-12-01), Hashiguchi
patent: 6778418 (2004-08-01), Meguro
patent: 7009433 (2006-03-01), Zhang et al.
patent: 2004/0135605 (2004-07-01), Chung et al.
patent: 0976021 (2000-02-01), None
Akui et al., “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor,” 2004 IEEE International Solid-State Circuits Conference, 10 pgs.
Sakiyama et al., “A Lean Power Management Technique: The Lowest Power Consumption for the Given Operating Speed of LSIs,” 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 99-100.
Suzuki et al., “A 300MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold-Voltage CMOS,” IEEE 1997 Custom Integrted Circuits Conference, pp. 587-590.
Macken et al., “FPM 15.2: A Voltage Reduction Technique for Digital Systems,” 1990 IEEE International Solid-State Circuits Conference, pp. 238-239.
Schmookler et al., “Leading Zero Anticipation and Detection—A Comparison of Methods,” 2001 IEEE, pp. 7-12.
Suzuki et al., “Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition,” IEEE Journal of Solid-State Circuits, vol. 31, No. 8 Aug. 1996, pp. 1157-1164.
Oklobdzija, “Comments on ‘Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition’,” IEEE Journal of Solid-State Circuits, vol. 32, No. 2, Feb. 1997, p. 292.
Oklobdzija, “An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, No. 1, Mar. 1994, pp. 124-128.
Callahan Timothy P.
Freescale Semiconductor Inc.
Hill Susan C.
King Robert L.
Nguyen Hai L.
LandOfFree
Delay circuitry and method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Delay circuitry and method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay circuitry and method therefor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3805135