Delay circuit with voltage compensation

Details Delay circuit with voltage compensation Delay circuit with voltage compensation

2000-06-26

2001-11-27

Nu Ton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S312000

Reexamination Certificate

active

06323712

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to delay circuits within an integrated circuit placed within a signal path to compensate for a delay difference of the signal path with another signal path to appropriately align arrival of signals on the separate signal paths. More particularly, this invention relates to delay circuits that have delays that are generally independent of the voltage level of the signals on the signal path.
2. Description of the Related Art
An integrated circuit is formed of many circuits performing sets of interdependent functions. For instance, in a Dynamic Random Access Memory (DRAM) the address signals arrive at a decode function to select the desired memory cell or cells to be read from or written to. At appropriate timing intervals the control signals, such as Row Address Strobe (RAS), Column Address Strobe (CAS), Chip Enable (CE), and clock, arrive at a control function that will generate the appropriate timing signals necessary to gate the word-line activation signals (WL
n
) to place a word-line signal on a desired row of an array of memory cells. The row of memory cells is activated, and in a read operation, a charge present within the memory cell flows to an attached bit-line. The voltage level present on the bit-line is determined by the level of charge within the memory cell. To sense the voltage level on a bit-line a sense amplifier must be activated at the correct time to sense the voltage level of the bit-line to determine the state of the data retained in the memory cell. The signals that activate the word-line decoder and the bit-line sense amplifier have a common initiation, but must occur at separate times. The timing for the two paths becomes critical.
One of the factors that influence the relative occurrence of the two signals is the voltage level of each signal. In one instance, the delay for one path, for example, the word-line decode and word-line activation, may be naturally insensitive to the voltage level of the signals traversing the path. However, the delay of the second path, in this case the sense line activation signal, may be dependent upon the voltage level of the signal.
Refer now to
FIG. 1
for a general discussion of the impact of the differences in delay of two signals. In
FIG. 1
, a first signal V
1
traverses a first delay circuit DC
1
, and a second signal V
2
traverses a second delay circuit DC
2
. The delayed version of the first signal V
1
d and the delayed version of the second signal V
2
d are combined in the functional block F
1
according to the function V
0
=H(V
1
, V
2
). Any variations in the delay of the first delay circuit DC
1
, or second delay circuit DC
2
due to voltage variations (either the power supply voltage level or the voltage levels of the first signal V
1
or the second signal V
2
affect the results of the output voltage V
0
of the functional circuit F
1
.
Refer to
FIG. 2
for further explanation of this effect. In
FIG. 2
, the delay of the first delay circuit DC
1
is designated d
1
and the delay of the second delay circuit DC
2
is designated d
2
. If the first delay is essentially dependent only on such parameters as the line resistance and parasitic capacitances such as for the word-lines and bit-lines of a DRAM memory array, the delay is relatively constant and can be accounted for. However, if the second delay circuit DC
2
is an active delay circuit used to compensate in the differences in time between the first signal V
1
, and the second signal V
2
, the second delay d
2
as explained hereinafter has a dependency on the voltage level of the second signal V
2
. When the variation in the voltage level of the second signal V
2
is too great, the delay d
2
of the second delay circuit may vary so as to corrupt the output voltage V
0
. In the example of a DRAM, the second delay circuit is an active delay circuit used to delay the sense amplifier activation signal until the voltage level on the bit-lines is set to indicate the level of charge present on the memory cell. If the voltage level of the original sense amplifier activation signal varies, then the magnitude of the delay time d
2
varies and the sense amplifier may sense the incorrect data.
Refer now to
FIG. 3
for a description of an active delay circuit. The basic active delay circuit consists of two inverters connected serially with the output of the first inverter I
1
connected to the input of the second inverter I
2
. The capacitor C
1
is connected to the junction of the output of the first inverter I
1
and the input of the second inverter I
2
. The input of the first inverter I
1
, receives the input signal V
IN
. The output A of the first inverter I
1
provides a voltage signal that is the inverse of the input signal V
IN
The transition time of the output A of the first inverter I
1
, is determined by the value of the capacitor C
1
.
The voltage level of the output V
0
at the second inverter I
2
is the inverse of the voltage level at the input of the second inverter I
2
. The threshold at which the output V
OUT
of the second inverter transitions between voltage levels is thus delayed by the change in transition time determined by the value of the capacitor C
1
.
The inverters I
1
and I
2
of
FIG. 3
a
are generally structured as shown in
FIG. 3
b
. The input terminal of the inverter is connected to the gates of the p-type metal oxide semiconductor (MOS) transistor P
1
and n-type (MOS) transistor N
1
. The source of the p-type MOS transistor P
1
is connected to the power supply voltage source V
DD
, and the source of the n-type MOS transistor N
1
is connected to the ground reference point. The drains of the p-type MOS transistor P
1
and the n-type MOS transistor N
1
are connected together to form the output terminal of the inverter. The output terminal is connected to a load capacitor C
L
that simulates the wiring capacitances and input capacitances of subsequent circuits.
The output voltage V
CL
at the output terminal during a transition from a low voltage level to a high voltage level is determined by the formula:
V
CL
=
Q
C
L
=
t
*
I
DSP
C
L
where:
Q is the charge present on the load capacitor.
C
L
is the value of the load capacitor.
t is the time of the transition of the output signal.
I
DSP
is the drain-to-source saturation current of the p-type MOS transistor P
1
and is proportional to the square of the input voltage V
IN
. That is:
I
DSN
=(V
DD
−V
IN(L)
)
2
.
Likewise, the voltage V
CL
at the output terminal during a transition from a high voltage level to a low voltage level is determined by the formula:
V
CL
=
Q
C
L
=
t
*
I
DSN
C
L
where:
I
DSN
is the drain-to-source saturation current of the n-type MOS transistor N
1
and is also proportional to the square of the input voltage V
IN
. That is:
I
DSN
=V
IN(L)
2
=V
DD
2
because V
in
=V
DD
when V
in
high.
FIG. 4
illustrates the plots of the waveforms at the input terminal V
IN
of the first inverter I
1
, the output A of the first inverter I
1
and the output V
OUT
of the second inverter I
2
. As described above, the output A of the first inverter I
1
has a transition from a high voltage level to a low voltage level that is proportional to the drain-to-source saturation current of the n-type MOS transistor N
1
and thus proportional to the square of the input voltage level V
IN
. A variation in the voltage level of the input voltage V
IN
causes a variation in the delay d
3
between the transition of the input voltage level V
IN
and the output voltage level V
OUT
.
Likewise, the output A of the first inverter I
1
has a transition from a low voltage level to a high voltage level that is proportional to the drain-to-source saturation current of the p-type MOS transistor P
1
and thus proportional to the square of the difference between the power supply voltage source V
DD
and the input voltage level V
IN
. Also, as stated above, any variation in the voltage level of the input voltage level V
IN
causes a variation in the delay between the transition o

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