Delay circuit with muting to prevent noise due to random data at

Details Delay circuit with muting to prevent noise due to random data at Delay circuit with muting to prevent noise due to random data at

1990-04-18

1991-12-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307596, 307602, 328 55, 328 60, 377 42, H03K 5159, H03K 301, H03K 2100

Patent

active

050737333

ABSTRACT:
A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter in the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.

REFERENCES:
patent: 3760280 (1973-09-01), Covington
patent: 4035661 (1977-07-01), Carlson
patent: 4468624 (1984-08-01), Rehbein
patent: 4553100 (1985-11-01), Nishiura

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