Delay circuit with field effect transistors

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307246, 307251, 307262, 307269, 307DIG4, H03K 1760, H03K 1728, H03K 513, H03K 5159

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active

041223616

ABSTRACT:
Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.

REFERENCES:
patent: RE27305 (1972-03-01), Polkinghorn et al.
patent: 3675043 (1972-07-01), Bell
patent: 3710271 (1973-01-01), Putman
patent: 3769528 (1973-10-01), Chu et al.
patent: 3806738 (1974-04-01), Chin et al.
patent: 3898479 (1975-08-01), Proebsting
patent: 3961269 (1976-06-01), Alvarez, Jr.
West, "Practical Circuit Design Using M.O.S.", Design Electronics (pub.); Mar., 1971; vol. 8, No. 6; pp. 30-32, 37, 38.
Anderson et al., "FET Inverter and Driver Circuit", IBM Tech. Discl. Bull.; vol. 16, No. 1, pp. 50-51; Jun., 1973.
Boss et al., "Powering Delay Circuit", IBM Tech. Discl. Bull.; vol. 16, No. 1, pp. 17-18; Jun., 1973.

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