Delay circuit with all-pass network

Details Delay circuit with all-pass network Delay circuit with all-pass network

1987-09-08

1989-08-01

Wan, Gene

Amplifiers

With semiconductor amplifying device

Including signal feedback means

330107, H03F 134

Patent

active

048536512

ABSTRACT:
A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, while between the second imputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.12), a fifth capacitor (C5) is arranged between the second inputs (26,28) of the second transconductor (G.sub.11) and the fourth transconductor (G.sub.13), and a sixth capacitor (C6) is arranged between the second inputs (25,28) of the first transconductor (G.sub.10) and the fourth transconductor (G.sub.13). The third (C3), fourth (C4) and sixth (C6) capacitors reduce resonance tendencies of the circuit and consequent resonant rise symptoms as a result of parasitic effects.

REFERENCES:
patent: 4745622 (1988-05-01), Gupta

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