Delay circuit with adjustable delay

Details Delay circuit with adjustable delay Delay circuit with adjustable delay

1990-11-27

1991-11-05

Hudspeth, David

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307608, 307594, H03K 513, H03K 5159

Patent

active

050633120

ABSTRACT:
A delay circuit with adjustable delay employs a switching flip-flop which includes a differential amplifier (A) having two outputs each one feedback-looped respectively onto two inputs, so as to produce the said switching. The looping is produced by a first (AD1) and a second (AD2) adder, each having a first, a second and a third input. The first inputs are connected to corresponding outputs of the differential amplifier to produce the feedback looping. The second inputs are intended to be connected respectively to a first and a second terminal delivering a signal to be delayed (V.sub.1.sup.+, V.sub.1.sup.-) and the third inputs receive respectively a first and a second control voltage (V.sub.3.sup.+, V.sub.3.sup.-). The delay is a function of the difference between the first and the second control voltage. The outputs of the adders are connected respectively to corresponding inputs of the differential amplifier.

REFERENCES:
patent: 4611136 (1986-09-01), Fujie
patent: 4795923 (1989-01-01), Dobos
patent: 4797586 (1989-01-01), Traa
patent: 4862020 (1989-08-01), Cowan et al.
patent: 4866314 (1989-09-01), Traa

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