Delay circuit using primarily a transistor's parasitic capacitan

Details Delay circuit using primarily a transistor's parasitic capacitan Delay circuit using primarily a transistor's parasitic capacitan

1989-06-30

1992-11-03

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307601, 307603, H03K 513, H03K 514

Patent

active

051608634

ABSTRACT:
A programmable delay line with digital input to a two-part digital-to-analog converter structure to define an equivalent resistance at a pull-down node. Preferred embodiments are configured as two identical halves. The outputs of the two halves are combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform.

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Mead et al., "Introduction to VLSI Systems", Oct. 80, pp. 11-14.
Hodges et al., "Analysis and Design of Digital Integrated Circuits", 1983, pp. 52-55.

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