Delay circuit used in semiconductor memory device

Details Delay circuit used in semiconductor memory device Delay circuit used in semiconductor memory device

1980-03-24

1983-08-30

Arnold, Bruce Y.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307601, 307607, H03K 513

Patent

active

044019041

ABSTRACT:
A random access read/write MOS memory device or the like employs a delay circuit in clock generators to produce small increments of delay. The delay circuit consists of a field effect transistor connected as a transfer device with its gate precharged and the gate-to-source capacitance much larger than the parasitics of the gate node. A larger transistor may be connected to the output node to improve the output waveform by holding down the output voltage at the beginning of a cycle.

REFERENCES:
patent: 3629618 (1971-12-01), Fujimoto
patent: 3665422 (1972-05-01), McCoy et al.
patent: 3903431 (1975-09-01), Heeren
patent: 3959781 (1976-05-01), Mehta et al.
patent: 4276487 (1981-06-01), Arzubi et al.

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