Delay circuit of clock synchronization device using delay...

Details Delay circuit of clock synchronization device using delay... Delay circuit of clock synchronization device using delay...

2002-05-06

2004-02-03

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S285000

Reexamination Certificate

active

06686788

ABSTRACT:

BACKGROUND OF INVENTION
1. Technical Field
A delay circuit for a clock synchronization device and, more particularly, a delay circuit for a clock synchronization device is disclosed having a positive feedback MOS cross-coupled delay cells and an operational amplifier and replica cell for controlling the delay cells.
2. Description of the Related Art
A general clock synchronization device such as a Delay Locked Loop (DLL) or a Phase Locked Loop (PLL) uses a Variable Delay Line (VDL) or a Voltage Controlled Oscillator (VCO). The VDL or VCO is constituted by a plurality of delay cells. The delay range of each delay cell is an important factor for determining the operation range of the clock synchronization device such as DLL or PLL.
There are generally a digital mode and an analog mode as operation modes for controlling the delay cells.
According to the digital mode, a desired delay time can be obtained by adjusting the number of the delay cells each having a fixed delay time. The precision in the digital mode is determined according to the fixed delay time of the delay cell. Accordingly this mode is unsuitable for a high-speed semiconductor memory device, which requires a high degree of precision. Also, since the operation range is proportional to the number of the delay cells, the delay cells are required in a large number to widen the operation range, thereby increasing the chip size. Moreover, the operation range is narrow and a jitter is large because the fixed delay time varies sensitive to the variation in Process, Voltage and Temperature (PVT).
Meanwhile, the analog mode sets a desired delay time through adjustment of an external control voltage because each delay cell thereof has a delay time variable to the control voltage. According to this mode, the chip size can be reduced since high precision is ensured and a wide working range can be obtained from a small sized delay cell.
FIG. 1
is a circuit diagram illustrating a detailed circuit of a conventional analog delay circuit.
The analog delay circuit includes an operational amplifier
1
for outputting a control voltage VBN by making the use of a reference voltage VREF. A delay unit
2
constituted by a plurality of delay cells DELCn is provided for delaying input signals VIN and /VIN for a predetermined delay time and then outputting signals VOUT and /VOUT by making the use of a control voltages VBN and VBP. A replica bias unit
3
having a constitution equivalent to that of the delay cells DELCn is included for outputting the output voltage VREP.
The operational amplifier
1
sets the level of the control voltage VBN according to a voltage difference between an output voltage VREP of the replica bias unit
3
, and the reference voltage VREF. Therefore, the operational amplifier
1
outputs the control voltage VBN, which is adjusted to be equivalent to a difference between the output voltage VREP of the replica bias unit
3
and the reference voltage VREF.
The delay cell DELC
1
of the delay unit
2
includes a variable current source
4
having a current value adjusted according to the control voltage VBN, an input block
5
for receiving input voltages VIN and /VIN, and a variable resistor block
6
having a resistance value adjusted according to the control voltage VBP.
In this case, the variable current source
4
is an NMOS transistor NMO having a gate connected to the control voltage VBN and a source connected to a ground voltage VSS.
The input block
5
is constituted by NMOS transistors NM
1
and NM
2
having their gates connected to input voltages VIN and /VIN, respectively. The NMOS transistors NM
1
and NM
2
have a common source connected to a drain of the NMOS transistor NMO.
The variable resistor block
6
is constituted by PMOS transistors PM
1
and PM
2
having their gates connected to the control voltage VBP. The PMOS transistors PM
1
and PM
2
have a common source connected to the supply voltage VDD. Here, the PMOS transistors PM
1
and PM
2
have their drains respectively connected to the drains of the NMOS transistors NM
1
and NM
2
.
The common drain of the NMOS transistor NM
1
forming the input block
5
and the PMOS transistor PM
1
forming the variable resistor block
6
and the common drain of the NMOS transistor NM
2
forming the input block
5
and the PMOS transistor PM
2
forming the variable resistor block
6
represent output terminals for respectively outputting signals VOUT and /VOUT.
In this case, the output signals VOUT and /VOUT of the (n−1)th delay cell DELC(n−1) are respectively applied to the input signals VIN and /VIN of the nth delay cell DELCn in the delay unit
2
. In this manner, the output signals VOUT and /VOUT of the nth delay cell DELCn are respectively inputted to the input signals VIN and /VIN of the (n+1)th delay cell DELC(n+1).
The replica bias unit
3
comprises a variable current source
7
having a current value adjusted according to the control voltage VBN, an input block
8
connected to the supply voltage VDD and the reference voltage VREF, and a variable resistor block
9
having a resistance value adjusted according to the control voltage VBP. In this case, all components of the replica bias unit
3
have the features equivalent to those of the delay cell DELC
1
. Therefore, if the control voltage VBN is outputted to set the level of the output voltage VREP of the replica bias unit
3
to that of the reference voltage VREF, the levels of the output signals VOUT and /VOUT of all of the delay cells DELC
1
are set to that of the reference voltage VREF. In this case, the reference voltage VBP is produced from a charge pump or a digital/analog converter DAC.
In the delay circuit of the clock synchronization device of the prior art as described above, the PMOS transistors PM
1
and PM
2
of the variable resistor block
6
as load transistors are required to operate in the linear range, so that the phase resolution of the delay circuit has the linear features. As a result, since the control voltage VBP has a narrow range the wording range becomes narrow.
SUMMARY OF DISCLOSURE
A delay circuit for a clock synchronization device is disclosed that has a plurality of delay cells each having a wide working range, thereby reducing the number of the delay cells and minimizing a phenomenon of jitter.
A delay circuit for a clock synchronization device is disclosed having a plurality of unit delay cells connected in series. Each of the unit delay cells comprise a variable current source having a current value adjusted according to a current control voltage; a variable resistance unit having a resistance value adjusted according to a resistance control voltage, wherein the variable resistance unit includes a cross-coupled adjustment device and outputs output signals through output terminals to a next unit delay cell; and an input device connected between the output terminals and the variable current source and configured to receive output signals from a previous unit delay cell.
Further disclosed is a delay circuit for a clock synchronization device comprising an operational amplifier configured to set a level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. Also included is a delay unit that includes a plurality of unit delay cells connected in series, each of the unit delay cells having a delay time that is set according to a resistance control voltage and the current control voltage. A replica bias unit is included and configured to output the regulation voltage according to the resistance control voltage and the current control voltage. Each of the plurality of unit delay cells further includes a first variable current source having a first current value adjusted according to the current control voltage; a first variable resistance unit having a first resistance value adjusted according to the resistance control voltage, wherein the first variable resistance unit includes a first cross-coupled adjustment device and outputs output signals through output terminals to a next unit dela

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