Delay circuit of a variable delay time

Details Delay circuit of a variable delay time Delay circuit of a variable delay time

1987-03-09

1989-04-11

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307606, 307605, 307594, 307595, 307452, 328 55, H03K 1728, H03K 522, H03K 19096, H03K 5159

Patent

active

048209430

ABSTRACT:
A delay circuit comprising a plurality of clocked inverters coupled cascade form. Each clocked inverter includes a plurality of MOS FETs. The circuit further comprises delay time-controlling MOS FETs connected in parallel to the MOS FETs of the clocked inverters, which are controlled by clock signals. When the delay time-controlling MOS FETs are turned on, the clocked inverters function as ordinary inverters. Conversely, when the delay time-controlling MOS FETs are turned off, the clocked inverters perform their own functions. Hence, one of two different delay times can be selected.

REFERENCES:
patent: 3989955 (1976-11-01), Suzuki
patent: 4445051 (1984-04-01), Elmasry
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4532439 (1985-07-01), Koike
patent: 4568842 (1986-02-01), Koike
Suzuki et al., "Clocked CMOS Calculator Circuitry," IEEE Journal of Solid-State Circuits, vol. SC-8, No. 6, pp. 462-469, Dec. 1973.

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