Delay circuit including first and second internal delay...

Details Delay circuit including first and second internal delay... Delay circuit including first and second internal delay...

2010-01-13

2011-11-22

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S142000, C327S161000, C327S198000, C327S395000

Reexamination Certificate

active

08063675

ABSTRACT:
Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor (17) (internal voltage (Va)) to increase from a ground voltage (VSS) to a voltage equal to or higher than an inverting threshold voltage of a constant current inverter (19) (threshold voltage (Vtn) of an NMOS transistor (16)). Therefore, the delay time period is determined with reference to the ground voltage (VSS). Note that the same holds true for an internal delay circuit (20). If the input signal (Vin) becomes High, the delay circuit utilizes the delay time period caused by an internal delay circuit (10). On the other hand, if the input signal (Vin) becomes Low, the delay circuit utilizes the delay time period caused by the internal delay circuit (20). Those internal delay circuit (10) and internal delay circuit (20) are identical with each other.

REFERENCES:
patent: 5532969 (1996-07-01), Houghton et al.
patent: 6044027 (2000-03-01), Zheng et al.
patent: 2002/0027465 (2002-03-01), Yoshikawa
patent: 2007-096661 (2007-04-01), None

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