Delay circuit having stable delay time

Details Delay circuit having stable delay time Delay circuit having stable delay time

1990-06-20

1991-10-15

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307542, 307558, 307585, 307594, 307597, H03K 513, H03K 508, H03B 104

Patent

active

050577220

ABSTRACT:
A delay circuit comprises a first inverter including a first MOSFET of a P-channel type having a gate connected to an input terminal, a drain connected to a first node and a source connected to a high voltage supply line; and a second MOSFET of an N-channel type having a gate connected to the input terminal, a drain connected through a first resistor to the first node and a source connected to ground. There is provided a current mirror circuit having an input side current path connected in parallel to the first MOSFET, and an output side current path connected between the first voltage supply line and a second node. A capacitor is connected between the second node and the ground, and there is provided a third MOSFET of the N-channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal, a drain connected to the second node and a source connected to the second voltage supply line. A second inverter includes a fourth MOSFET of the P-channel type having a gate connected to the second node, a drain connected to an output terminal and a source connected to the high voltage supply line, and a fifth MOSFET of the N-channel type having a gate connected to the input terminal, a drain connected through a second resistor to the output terminal and a source connected to the ground.

REFERENCES:
patent: 4837466 (1989-06-01), Kanauchi
patent: 4947064 (1990-08-01), Kim et al.

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