Delay circuit having delay time period determined by discharging

Details Delay circuit having delay time period determined by discharging Delay circuit having delay time period determined by discharging

1985-11-08

1987-02-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307571, 307605, H03K 1756, H03K 17687

Patent

active

046441824

ABSTRACT:
A delay circuit including: a P-channel enhancement-type transistor (Q.sub.11), linked between an input terminal (IN) and an output terminal (OUT); a capacitor (C) connected to the gate of the transistor (Q.sub.11); a charging switch (SW.sub.1) for charging the capacitor (C); a discharging switch (SW.sub.2) for discharging the capacitor (C); and a control circuit (CONT) for controlling the charging switch (SW.sub.1) and the discharging switch (SW.sub.2). The delay time period is determined by the discharging operation of the discharging switch (SW.sub.1) after the charging operation of the charging switch (SW.sub.1).

REFERENCES:
patent: 3740581 (1973-06-01), Pfiffner
patent: 4061929 (1977-12-01), Asano
patent: 4529897 (1985-07-01), Suzaki et al.

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