Delay circuit having delay time adjustable by current

Details Delay circuit having delay time adjustable by current Delay circuit having delay time adjustable by current

2000-09-05

2003-12-02

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S262000, C327S263000

Reexamination Certificate

active

06657473

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a delay circuit, and a semiconductor device and semiconductor integrated circuit equipped with the delay circuit. More particularly, the present invention is concerned with a delay circuit having a delay time that can be adjusted by a control current, and a semiconductor device and a semiconductor integrated circuit equipped with such a delay circuit.
2. Description of the Related Art
Generally, semiconductor devices are required to accurately operate over a wide frequency range. Generally, the semiconductor devices are equipped with a delay circuit that adjusts the timing relationship among internal signals or the timing relationship between an external clock and an internal clock. Such a delay circuit is required to delay a signal over a wide frequency range with a high precision.
Conventionally, the delay circuit includes logic circuits connected in series, each logic circuit being made up of logic gates such as an inverter and a NAND gate. Each of the logic circuits acts to delay a signal applied to the delay circuit. The delay of time depends on the number of cascaded logic circuits through which the input signal serially passes. That is, the delay time can be adjusted by changing the number of logic circuits (the number of stages) through which the input signal serially passes. Thus, the delay time is proportional to the number of logic circuits through which the input signal serially passes.
The minimum adjustable delay time is equal to the delay time of one logic circuit or delay stage. In other words, the minimum precision of the delay circuit depends on the delay time of one logic circuit. Thus, it is impossible to more finely adjust the delay time than the precision of each logic circuit.
There is a demand for a delay circuit capable of delaying a signal over a wide frequency range with high precision in order to realize fine adjustment of the timing relationship among the internal signals of the semiconductor device and the timing relationship between the external and internal clocks.
There is another demand as described below. There are semiconductor integrated circuits equipped with a circuit that internally generates a reference voltage. A transient noise may be superimposed on the reference voltage. Such a transient noise prevents the semiconductor integrated circuit from operating in a stable state. Hence, it is required to avoid an influence of the transient noise.
For example, a low-pass filter is provided between a reference voltage generating circuit and a circuit which utilizes a reference voltage generated by the reference voltage generating circuit. The low-pass filter smoothes the transient noise. However, there is a disadvantage in that the low-pass filter degrades responsibility to a change of the reference voltage. Thus, the use of the low-pass filter is not adequate for a situation in which the reference voltage changes. That is, the conventional semiconductor integrated circuit does not have any effective means for filtering the transient noise superimposed on the reference signal that changes.
SUMMARY OF THE INVENTION
It is a general object of the present invention to eliminate the above disadvantages.
A more specific object of the present invention is to provide a delay circuit capable of adjusting a signal over a wide frequency range with high precision so that the timing relationship between signals can be finely adjusted and to provide a semiconductor device equipped with such a delay circuit.
The above objects of the present invention are achieved by a delay circuit comprising: a delay part delaying a signal by a delay time which can be varied based on a control current; and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.
Another object of the present invention is to provide a semiconductor integrated circuit capable of operating in a stable state in a situation in which a transient noise is superimposed on a reference voltage that is generated in the semiconductor integrated circuit.


REFERENCES:
patent: 5355038 (1994-10-01), Hui
patent: 5463343 (1995-10-01), Marbot
patent: 5506534 (1996-04-01), Guo et al.
patent: 6166576 (2000-12-01), Stave
patent: 6262616 (2001-07-01), Srinisavan et al.
patent: 6348827 (2002-02-01), Fifield et al.

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