Delay circuit for gate-array LSI

Details Delay circuit for gate-array LSI Delay circuit for gate-array LSI

1985-08-20

1987-10-13

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307451, 307585, 307594, 307603, 307279, H03K 19094, H03K 17284, H03K 17687, H03K 3353

Patent

active

047000899

ABSTRACT:
A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q.sub.1p to Q.sub.4p) and a plurality of N-channel transistors (Q.sub.1n to Q.sub.4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.

REFERENCES:
patent: 4395774 (1983-07-01), Rapp
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4476401 (1984-10-01), Lin
patent: 4490629 (1984-12-01), Barlow et al.
patent: 4518873 (1985-05-01), Suzuki et al.
patent: 4532439 (1985-07-01), Koike
patent: 4539489 (1985-09-01), Vaughn
patent: 4563594 (1986-01-01), Koyama
patent: 4571504 (1986-02-01), Iwamoto et al.

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