Delay circuit for digital signals

Details Delay circuit for digital signals Delay circuit for digital signals

1985-11-05

1988-07-26

Harkcom, Gary V.

Boots, shoes, and leggings

364715, G06F 738

Patent

active

047605421

ABSTRACT:
A digital delay arrangement generates a delay time which is a noninteger multiple of the period of a system clock frequency. The arrangement includes a digital delay circuit having a delay time equal to the period, a multiplier for the part of the noninteger multiplier, b, being less than one, a further multiplier for 1- b, an adder and a peaking filter clocked by the system clock.

REFERENCES:
patent: 3521041 (1970-07-01), Blerkom et al.
patent: 3943346 (1976-03-01), Urkowitz et al.
patent: 4044241 (1977-08-01), Hatley, Jr.
patent: 4074308 (1978-02-01), Gibson
patent: 4472785 (1984-09-01), Kasupa
patent: 4531221 (1985-07-01), Chung et al.
patent: 4542475 (1985-09-01), Acampora
patent: 4584600 (1986-04-01), Baker
patent: 4649507 (1987-03-01), Inaba et al.
Rossi, "Digital Television Image Enhencement", Journal of the Society of Motion Picture & Television Engineers, vol. 84, No. 7, Jul. 1975, pp. 545-551.

Affiliated with

Also associated with

Rating

Delay circuit for digital signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay circuit for digital signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay circuit for digital signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-262062