Delay circuit for delaying an output signal relative to an input

Details Delay circuit for delaying an output signal relative to an input Delay circuit for delaying an output signal relative to an input

1989-02-21

1992-03-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307595, 307597, 307602, 307605, H03K 513

Patent

active

050971590

ABSTRACT:
A delay circuit having two or more first switching transistors connected in series between an output terminal and a power source line, and two or more second switching transistors connected in series between the output terminal and another power source line, the first and the second switching transistors operating in a complementary manner in response to an input signal, one or more nodes of each switching transistor being connected by one or more current paths each connecting at least one capacitor, whereby an input signal is transmitted to the output terminal at a specified interval defined by the capacitance of the capacitor.

REFERENCES:
patent: 4700089 (1987-10-01), Fujii et al.
patent: 4868627 (1989-09-01), Yamada et al.
Grimes, "Signal Transition Detector", IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, pp. 3905-3906.
"Device Parameter Independent Delay Circuit", IBM Technical Disclosure Bulletin, vol. 31, No. 1, Jun. 1988, pp. 21-23.

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