Delay circuit for changeably delaying an analog signal

Amplifiers – With semiconductor amplifying device – Including frequency-responsive means in the signal...

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330304, H03F 354

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active

053610431

ABSTRACT:
A delay circuit is provided with an npn type of transistor of which a base is connected to an input terminal, a first constant current source through which a constant current flows from an emitter of the transistor to ground, a first capacitor arranged between the emitter of the transistor and an electric source terminal, a second capacitor C.sub.22 arranged between a collector of the transistor and an output terminal, a first resistor arranged between the emitter of the transistor and the output terminal, a second resistor arranged between the collector of the transistor and the electric source terminal. The constant current of the constant current source is changeable, and an emitter resistance of the transistor is changed depending on the constant current. Therefore, an analog signal applied to the input terminal is changeably delayed by coaction of the resistors, the capacitors and the emitter resistance adjusted by changing the constant current of the constant current source.

REFERENCES:
patent: 3800265 (1974-03-01), Yoshioka
Elektor vol. 1, No. 5, p. 720 Jul./Aug. 1975.
Elektor vol. 3, No. 2, p. 31 Feb. 1975.
"Design of an Operational Amplifier Circuit" by N. Fujii; Electronic Science Series-74; pp., 163-175; published Aug. 30, 1977 (w/partial English translation).

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