Delay circuit for a monolithic integrated circuit and method for

Details Delay circuit for a monolithic integrated circuit and method for Delay circuit for a monolithic integrated circuit and method for

1986-02-10

1990-01-16

Tarcza, Thomas H.

Boots, shoes, and leggings

307597, 307603, 328 55, 328 78, H03K 513

Patent

active

048947911

ABSTRACT:
A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable. A method for economically adjusting the delay of each of many like delay circuits embodied in a semiconductor wafer includes measuring a sample of the delays of the delay circuits, calculating an average delay, determining the difference between a desired delay and the average delay to determine an incremental amount of delay to eliminate or to add, determining from predetermined data which fusible links should be opened, and using a laser beam to open the appropriate links.

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