Delay circuit device

Details Delay circuit device Delay circuit device

1999-12-14

2001-06-19

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S161000

Reissue Patent

active

RE037232

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device, and particularly to a delay circuit device for use in generating transmitting or controlling synchronous signals (hereinafter referred to as “clock pulse”).
2. Description of the Related Art
As shown in
FIG. 1
, a semiconductor circuit device using clock pulses according to the prior art receives an external clock pulse
401
at reception circuit
402
, amplifies the clock pulse at an amplification circuit
403
, and generates an internal clock pulse
405
for use in circuit
404
. As a result, in the process of receiving at reception circuit
402
and amplifying at amplification circuit
403
, a delay time
406
is produced between the external clock
401
and the internal clock
402
, as shown in FIG.
2
. This delay time
406
tends to increase with increased circuit scale of semiconductor circuit devices achieved through progress in manufacturing techniques and the growing diameter of semiconductor substrates. On the other hand, with the increase in speed of systems mounted in semiconductor circuit devices, circuit operation as well as the clock pulses employed are also increasing in speed. This increase in speed results in an increase in delay time
406
in relation to the clock cycle
407
, and presents obstacles to circuit operation.
As a countermeasure, Phase-Locked Loops (hereinafter abbreviated as “PLL”) have come into use.
FIG. 3
shows the basic circuit structure of a PLL. At phase comparator
504
, a phase error signal
506
is outputted from the phase difference of an external clock pulse
501
entering via reception circuit
502
and an internal clock pulse
505
via a delay circuit
503
having a delay equivalent to that of reception circuit
502
. Phase error signal
506
becomes control signal
508
after passing through loop filter
507
, and is inputted to voltage-controlled oscillator
509
. At voltage-controlled oscillator
509
, a clock pulse
510
is generated having a frequency corresponding to control signal
508
. Clock pulse
510
is amplified at amplification circuit
511
to become internal clock pulse
505
for use in clock-controlled circuit
512
. Control signal
508
controls voltage-controlled oscillator
509
such that the phase difference between external clock pulse
503

501

and internal clock pulse
505
is eliminated, and controls voltage-controlled oscillator
509
until a phase difference is no longer detectable.
In a PLL, the delay of the internal clock pulse with respect to the external clock pulse therefore disappears, and the problem of obstacles to circuit operation due to the relative increase in delay time with respect to clock cycle can thus be avoided.
A configuration incorporating a frequency-dividing circuit in a PLL such as shown in
FIG. 4
has come to be used in semiconductor circuit devices employing a clock pulse that has an integer duty ratio or a frequency that is an integer power of the frequency of an external clock.
In phase comparator
504
, a phase error signal
506
is outputted from the phase difference between an external clock pulse
501
entering via reception circuit
502
and an internal clock pulse
505
entering via delay circuit
503
having a delay equal to that of reception circuit
502
. Phase error signal
506
passes through loop filter
507
to become control signal
508
and is inputted to voltage-controlled oscillator
509
. Voltage-controlled oscillator
509
generates a clock pulse
510
having a frequency that corresponds to control signal
508
. Clock pulse
510
passes through frequency divider circuit
513
where it undergoes frequency division to become clock pulse
514
. Clock pulse
514
is amplified by amplification circuit
511
to become the internal clock pulse
505
used by clock-controlled circuit
512
, and clock pulse
510
is amplified by amplification circuit
515
to become the internal clock pulse
516
used by clock-controlled circuit
512
. Control signal
508
controls voltage-controlled oscillator
509
so as to eliminate the phase difference between external clock pulse
503

501

and internal clock pulse
505
. Internal clock pulse
505
becomes a clock pulse having the same phase and cycle as external clock pulse
503
, and moreover, having an integer duty ratio. Clock
516
has the same frequency as internal clock pulse
505
before frequency division, and therefore, becomes a clock pulse having a frequency-divided inverse frequency with respect to external clock pulse
503

501
.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a delay circuit device that solves the following drawbacks of a circuit employing the above-described PLL:
1. Time (in excess of several tens of cycles) is required to eliminate the phase difference between the internal clock pulse and external clock pulse.
2. As a result of drawback
1
, the PLL must always be operated to provide an internal clock pulse having no phase difference with the external clock pulse at a desired timing, thereby increasing power consumption.
3. Because a voltage-controlled oscillator controls oscillation by voltage, the amplitude of the control voltage drops with a decrease in power source voltage, thereby degrading the accuracy of the controlled frequency.
4. To maintain the accuracy of a fixed controlled frequency when controlling clock pulses over a wide range of frequencies, a plurality of voltage-controlled oscillators having differing frequency ranges must be used, and time is required to eliminate phase difference when voltage-controlled oscillators are switched.
5. Because the conditions used to eliminate phase difference are limited (voltage, device items), often problematic preliminary investigations must be carried out.
6. Many varieties of circuits exist, and it is difficult to deal with defective circuits.
According to the present invention, a delay circuit device is provided which includes a first delay circuit series that can extract output from any position on a transmission path of a signal, a second delay circuit series that can enter input from any position on a transmission path of a signal, and a control circuit having an input terminal, an output terminal, and an input/output control terminal for signals; wherein the first delay circuit series and the second delay circuit series are arranged such that their signal transmission paths are aligned in opposite directions; output of the first delay circuit series and input of the second delay circuit series being passed through the control circuit and sequentially connected to each other from the side close to the input of the first delay circuit series and from the side close to the output of the second delay circuit series; and wherein a first signal is inputted to the first delay circuit series, a second signal is inputted to the control circuit at any time thereafter, and the first signal in the first delay circuit series is transferred to the second delay circuit series.
According to an embodiment of the present invention, the second signal is inputted to the control circuit, the first signal on the first delay circuit series is transferred to the second delay circuit series, and the first signal on the first delay circuit series is removed from the first delay circuit series.
According to another embodiment of the present invention, the first delay circuit series and the second delay circuit series are constructed such that the delay times of both series are equal.
According to another embodiment of the present invention, voltage impressed to the first delay circuit series and the second delay circuit series is supplied from a constant-voltage power source.
According to another embodiment of the present invention, in a circuit having a plurality of voltage sources, the voltage impressed to the first delay circuit series and the second delay circuit series is supplied from a relatively high voltage source.
According to another embodiment of the present invention, a delay circuit device includ

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