Delay circuit constituted by MISFETs

Details Delay circuit constituted by MISFETs Delay circuit constituted by MISFETs

1979-07-12

1982-07-13

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307577, 307482, 307594, H03K 326, H03K 1901

Patent

active

043396720

ABSTRACT:
A delay circuit includes first and second MISFETs and a capacitance element connected to the common juncture of the first and the second MISFETs. The electricity of the capacitance element is charged through the first MISFET and is discharged through the second MISFET. Since the first and the second MISFETs effectively perform a push-pull operation, a signal of a predetermined level and a predetermined delay time to be delivered to a circuit having a logic threshold voltage is derived from the common juncture.

REFERENCES:
patent: 3980896 (1976-09-01), Kato
patent: 3986046 (1976-10-01), Wunner
patent: 4011467 (1977-08-01), Shimada et al.
patent: 4071783 (1978-01-01), Knepper
patent: 4217502 (1980-08-01), Suzuki et al.

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