Delay circuit arrangement for use in a DAC/driver waveform...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

Reexamination Certificate

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Details

C327S100000, C327S563000

Reexamination Certificate

active

06249164

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communications network in general and, in particular, to circuit arrangements for generating signals for transmission on said communications network.
2. Prior Art
The use of circuit arrangements to generate signal waveforms is well known in the prior art. The signal waveforms can be used to transmit information on busses, communications media and/or control writing and/or reading information into/from memories. Usually, the signal waveforms are in the form of voltages.
Several design criteria have to be addressed in order to provide acceptable waveform generating circuits. For example, if the waveforms are to be used in transmitting information in a computer network, the transmission system, such as Local Area Network, etc., interconnecting the computers has to be addressed in order to design an acceptable waveform generating circuit. Usually, the characteristics, such as voltage waveforms electromagnetic emissions of the interconnecting network are set by standards. In order to be compliant, the designer is faced with the problem of adapting technologies to meet the standard requirements.
Another area of challenge is to minimize product cost. It is well recognized and understood that the low cost producer of quality products will have substantial advantages in the marketplace. One of the many ways of reducing cost is to integrate analog and digital circuits on the same substrate. The cost savings are even more substantial if the VLSI manufacturing process is friendly to the fabrication of both analog and digital devices.
Prior art approaches in developing waveform generating circuits heavily relied on magnetics or other analog techniques to provide desired wave shape. The magnetics are usually expensive and requires tuning. The net result is that the cost of the product is unnecessarily increased.
Even when the prior art uses on chip circuits, to generate a desire wave shape, the circuits usually have a high degree of analog contents and, as such, are not easily adapted to digital processes such as CMOS technology.
Examples of the prior art techniques and devices are set forth in the below listed patents.
U.S. Pat. No. 5,440,514 describes a memory with a write control delay locked loop for controlling a write cycle of the memory. The delay locked loop avoids the race condition by adjusting the write cycle time of the memory so that if one part of the write cycle timing is increased, all of the write timing margins are increased.
U.S. Pat. No. 5,563,526 describes a programmable mixed mode integrated circuit in which analog and digital circuits are provided on the same chip. The analog circuits are fabricated from traditional analog devices. Thus, it appears as if the chip could not be manufactured by a straightforward digital process.
U.S. Pat. No. 5,687,330 describes a driver circuit for a bus in which the rise and fall of the output signal from the driver circuit is controlled by a register external to the driver circuit.
Still other prior art patents relating to waveform generation includes U.S. Pat. Nos. 5,185,538; 5,440,515; 5,479,124 and 5,684,064. Even though the patents are believed to work well for their intended purposes, they do not address the problems discussed above or control wave shaping as tightly as it is controlled by the present invention.
For high speed (100 Mbps through gigabits) data transmissions, it is imperative that the waveform be tightly controlled or else the require data speed cannot be attained. Consequently, there is a need for a circuit arrangement that provides tightly controlled waveforms.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a delay circuit arrangement that is more efficient than has heretofore been possible.
It is another object of the present invention to provide a delay cell ideal for use in a phase lock loop including a delay line configured as a ring oscillator.
This is made possible by circuitry that alters the P-Channel currents and differential voltage swing inside a differential delay cell.
In particular, the delay circuit arrangement includes a delay cell and controller. The delay cell includes a differential pair of N-Channel devices and P-Channel devices coupling the differential pair to positive voltage rail. The controller provides conductivity adjustment in the P-Channel devices. Adjustment of the delay is made by adjusting the current in a device biased in its linear region and coupling the differential devices to a ground potential.


REFERENCES:
patent: 4994730 (1991-02-01), Rossi et al.
patent: 5180995 (1993-01-01), Hayashi et al.
patent: 5185538 (1993-02-01), Kondoh et al.
patent: 5440514 (1995-08-01), Flannagan
patent: 5440515 (1995-08-01), Chang et al.
patent: 5442629 (1995-08-01), Geyer et al.
patent: 5479124 (1995-12-01), Pun et al.
patent: 5563526 (1996-10-01), Hastings et al.
patent: 5568064 (1996-10-01), Beers et al.
patent: 5608876 (1997-03-01), Cohen et al.
patent: 5687330 (1997-11-01), Gist et al.

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