Delay circuit and semiconductor integrated circuit having same

Details Delay circuit and semiconductor integrated circuit having same Delay circuit and semiconductor integrated circuit having same

2000-06-27

2002-04-09

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S276000

Reexamination Certificate

active

06369627

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay circuit and a semiconductor integrated circuit operating in synchronization with a clock. More particularly, it relates to a semiconductor integrated circuit implementing a delay locked loop (DLL) circuit for synchronizing an internal clock signal for use in the interior circuit with an external clock signal supplied from the exterior.
2. Description of the Related Art
Synchronous DRAMs (SDRAMs), double data rate synchronous DRAMs (DDR-SDRAMs), and the like are known as the semiconductor integrated circuits operating in synchronization with a clock. In the semiconductor integrated circuits of this type, the interior circuit is operated in synchronization with the clock signal supplied from the exterior, for data input/output. In general, the semiconductor integrated circuit has a plurality of data output terminals. The output data output from these output terminals has skews in accordance with the wiring length of the signal lines depending on the circuit layout on the chip. The skews relatively increase with higher frequency the clock having. Recently, the skew mentioned above has become a big problem which can not be ignored since SDRAMs and DDR-SDRAMs having an operating frequency over 100 MHz have been developed.
In order to reduce such skews, there has been developed a semiconductor integrated circuit implementing a DLL circuit. The DLL circuit adjusts the phase of an internal clock signal to be used in the interior circuit to a predetermined phase of the reference clock signal supplied from the exterior. Its basic configuration has been disclosed, for example, in Japanese Patent Laid-Open Publication No. Hei 10-112182.
Moreover, there has been proposed a DLL circuit comprising a rough delay circuit having rougher units for delay time adjustment and a fine delay circuit having finer units for delay time adjustment. The DLL circuit of this type can improve the precision of the phase adjustment and reduce jitter in the internal clock signal as well.
FIG. 1
shows an example of the semiconductor integrated circuit implementing the DLL circuit proposed by the present applicant. Incidentally, the circuit shown in
FIG. 1
has not publicly known.
This semiconductor integrated circuit comprises: an input buffer
1
for outputting a clock signal CLK accepted from the exterior as an internal clock signal ICLK; a delayed clock generator
2
for generating an internal clock signal ICLK
2
delayed by a predetermined time from the internal clock signal ICLK; an output buffer
3
for outputting a data signal DATA read out from a memory cell or the like as an output signal DOUT in synchronization with the internal clock signal ICLK
2
; a phase control unit
4
for adjusting the phase of the internal clock signal ICLK
2
to the phase of the clock signal CLK; and a start signal generator
5
for generating a start signal START for synchronizing the operations of the delayed clock generator
2
and the phase control unit
4
.
The delayed clock generator
2
comprises a rough variable delay circuit
6
and a fine variable delay circuit
7
.
The rough variable delay circuit
6
, constituted by cascading a plurality of delay stages (not shown) having longer delay time, is a circuit for making a rough adjustment to delay time in accordance with the number of delay stages connected. Under the control of a rough delay control circuit
13
, the rough variable delay circuit
5
upshifts or downshifts to increase or decrease the number of delay stages connected.
The fine variable delay circuit
7
, constituted by cascading a plurality of delay stages (not shown) having shorter delay time, is a circuit for making a fine adjustment to delay time in accordance with the number of these delay stages connected. Under the control of a fine delay control circuit
15
, the fine variable delay circuit
7
increases (upshifts) or decreases (downshifts) the number of delay stages connected. The maximum delay time of the fine variable delay circuit
7
is somewhat longer than the delay time of one delay stage in the rough variable delay circuit
6
.
The phase control unit
4
comprises frequency dividers
8
and
9
, a dummy output buffer
10
equivalent to the output buffer
3
, a dummy input buffer
11
equivalent to the input buffer
1
, a rough phase comparator
12
, the rough delay control circuit
13
, a fine phase comparator
14
, the fine delay control circuit
15
, a stage number setting circuit
16
, a stage number detector
17
, and a DLL control circuit
18
.
The frequency divider
8
divides the frequency of the internal clock signal ICLK to generate an internal clock signal /CLK
1
, and outputs the same to the rough phase comparator
12
and the fine phase comparator
14
. Here, “/” employed in the clock signal /CLK
1
or the like indicates a logic inversion with respect to the clock signal CLK.
The frequency divider
9
divides the frequency of the internal clock signal ICLK
2
to generate an internal clock signal ICLK
3
, and outputs the same to the dummy output buffer
10
. The frequency dividers
8
and
9
have a dividing rate of 1/4, for example. The frequency division of the clock signals ICLK and ICLK
2
facilitates the phase comparison at higher frequency as well as reduces the power consumption.
The signal output from the dummy output buffer
10
is supplied to the dummy input buffer
11
, and output to the rough phase comparator
12
and the fine phase comparator
14
as an internal clock signal DICLK.
The stage number setting circuit
16
has a delay circuit equivalent to one delay stage in the rough variable delay circuit
6
and a delay circuit equivalent to one delay stage in the fine variable delay circuit
7
. The stage number setting circuit
16
always monitors how many stages of the fine variable delay circuit
7
corresponds to the delay time of one delay stage in the rough delay control circuit
6
, and outputs the number of stages to the fine delay control circuit
15
and the stage number detector
17
as a maximum stage number signal J
2
. The maximum stage number signal J
2
varies with the operating voltage and the ambient temperature of the semiconductor integrated circuit.
The stage number detector
17
has the function of receiving a stage number signal J
1
, which is the number of delay stages used in the fine variable delay circuit
7
, and the maximum stage number signal J
2
. It respectively outputs an overflow signal OF and an underflow signal UF when the stage number signal J
1
becomes the maximum stage number signal J
2
and the stage number signal J
1
reaches the minimum value.
The DLL control circuit
18
receives a phase coincidence signal JSTR from the rough phase comparator
12
, receives the overflow signal OF and the underflow signal UF from the stage number detector
17
, and outputs select signals S
1
and S
2
, a shift-up signal UP, and a shift-down signal DOWN. The DLL control circuit
18
activates the select signal S
1
and inactivates the select signal S
2
when the phase coincidence signal JSTR is inactive, and inactivates the select signal S
1
and activates the select signal S
2
when the phase coincidence signal JSTR is active. The DLL control circuit
18
also outputs the shift-up signal UP to the rough phase comparator
12
on receiving the overflow signal OF, and outputs the shift-down signal DOWN to the rough phase comparator
12
on receiving the underflow signal UF.
The rough phase comparator
12
receives the activated select signal S
1
, compares the phases of the internal clock signal /CLK
1
and the internal clock signal DICLK, and outputs the comparison result to the rough delay control circuit
13
. The rough phase comparator
12
activates the phase coincidence signal JSTR when the internal clock signal DICLK and the internal clock signal /CLK
1
coincide with each other in phase, upshifts the rough variable delay circuit
6
on receiving the shift-up signal UP, downshifts the rough variable delay circuit
6
on receiving the shift-do

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