Delay circuit and semiconductor device using the same

Details Delay circuit and semiconductor device using the same Delay circuit and semiconductor device using the same

2002-04-04

2004-06-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S210000, C327S391000, C327S392000, C326S024000, C326S087000

Reexamination Certificate

active

06753707

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to a delay circuit used in a semiconductor device.
BACKGROUND OF THE INVENTION
A delay circuit is designed to produce an output signal that is delayed intentionally with respect to an input signal. A conventional delay circuit includes a plurality of inverters, which are serially connected between an input terminal and an output terminal. Another conventional delay circuit includes a resistor and a capacitor, which are connected between an input terminal and an output terminal.
According to conventional delay circuits, a delay time may not be uniform. Further, a through-current or leak current is generated, and as a result, it is difficult to decrease a power consumption.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a delay circuit, which produces a respected delay time reliably.
Another object of the present invention is to provide a delay circuit, in which the amount of through-current or leak current flowing through an output circuit is reduced.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a delay circuit includes a first input circuit, which receives an input signal; and an output circuit which comprises first and second output elements to supply an output signal. The first and second output elements are connected serially between a first power supply source and a second power supply source. The delay circuit further includes a delay element, which is coupled between the input circuit and output circuit to generate a first control signal that is delayed with respect to the input signal. The delay circuit still further includes a first node coupled between the delay element and one of the first and second output elements; and a second node which is coupled to the other output elements to supply a second control signal having substantially no delay with respect to the input signal.
According to the present invention, the control gate is turned off even if the delay node is at an intermediate level, so that a respected delay time can be provided reliably. Further, the amount of leak current or through-current flowing through the output circuit is reduced.


REFERENCES:
patent: 5023472 (1991-06-01), Hasimoto et al.
patent: 5120992 (1992-06-01), Miller et al.
patent: 5355028 (1994-10-01), O'Toole
patent: 5357211 (1994-10-01), Bryson et al.
patent: 5550501 (1996-08-01), Ito et al.
patent: 5907254 (1999-05-01), Chang
patent: 6198334 (2001-03-01), Tomope et al.
patent: 6400176 (2002-06-01), Griffin et al.
patent: 6462597 (2002-10-01), Lee
patent: 02-017717 (1990-01-01), None

Affiliated with

Also associated with

Rating

Delay circuit and semiconductor device using the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay circuit and semiconductor device using the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay circuit and semiconductor device using the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3344372