Delay circuit and ring oscillator incorporating the same

Details Delay circuit and ring oscillator incorporating the same Delay circuit and ring oscillator incorporating the same

2001-09-05

2002-06-04

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000

Reexamination Certificate

active

06400201

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an I
2
L delay circuit and a ring oscillator incorporating the same.
BACKGROUND OF THE INVENTION
FIG. 17
shows a delay circuit arranged in a conventionally known manner. In
FIG. 17
, reference numeral
1701
denotes a first I
2
L inverter,
1702
a second I
2
L inverter, and
1703
a capacitor. The delay introduced by the delay circuit of
FIG. 17
is a time taken for the input terminal voltage of the I
2
L inverter
1702
(the voltage across the capacitor
1703
) to grow to the threshold voltage of the I
2
L inverter
1702
as the capacitor
1703
coupled to the input of the I
2
L inverter
1702
is charged by the input terminal current of the I
2
L inverter
1702
. The input terminal current of the I
2
L inverter
1702
is the collector current of a laterally structured p-n-p I
2
L transistor constituting the I
2
L inverter
1702
and is an injection current of the I
2
L inverter
1702
.
Japanese Laid-Open Patent Application No. 9-172356/1997 (Tokukaihei 9-172356; published on Jun. 30, 1997) discloses a delay circuit capable of introducing variable delays. The delay circuit, including a plurality of inverting buffers and switches as shown in
FIG. 18
, alters the delay through the control of the switches.
In
FIG. 18
, reference numeral
1804
denotes a first inverting buffer,
1801
a
a second inverting buffer,
1801
b
a third inverting buffer,
1801
c
a fourth inverting buffer,
1801
d
a fifth inverting buffer,
1802
a
a first switch,
1802
b
a second switch,
1802
c
a third switch,
1802
d
a fourth switch, and
1803
a capacitor. At least one of the first to fourth switches
1802
a
-
1802
d
is closed at any given time.
A distinction of the delay circuit in
FIG. 18
lies in that the number of inverting buffers (other than the first inverting buffer
1804
and the second inverting buffer
1801
a
) involved in charging/discharging of the capacitor
1803
is changed through the opening/closing of the second to fourth switches
1802
b
-
1802
d
connected in series with the respective third to fifth inverting buffers
1801
b
-
1801
d
to produce delays of various values.
Specifically, in the delay circuit of
FIG. 18
, the more the connected inverting buffers, the greater the current for charging/discharging the capacitor
1803
. Therefore, the delay can be varied by altering the number of the inverting buffers.
The foregoing prior art has following problems.
In the delay circuit of
FIG. 17
, if the capacitor
1703
is integrated in an integrated circuit (not shown), the capacitance (electrostatic capacitance) of the capacitor
1703
, and hence the delay, become invariable. By contrast, if the capacitor
1703
is provided external to the integrated circuit, the delay is variable by changing the capacitance of the capacitor
1703
; nevertheless, the need arises to dispose the capacitor
1703
externally to the integrated circuit and to equip the integrated circuit with a terminal at which the integrated circuit is coupled to the capacitor
1703
. These requirements cause serious problems in mounting of the integrated circuit.
In the delay circuit of
FIG. 18
, the second to fifth inverting buffers
1801
a
-
1801
d
involved in charging/discharging of the capacitor
1803
need be arranged to include a current supply (not shown) and require an equal number of switches (
2
a
-
2
d
), which renders the actual circuit configuration complex.
In addition, to obtain a substantially long delay, either the capacitance of the capacitor
1803
must be sufficiently large or the charge current of the capacitor
1803
must be sufficiently small. Integration of a large capacitance capacitor
1803
in an integrated circuit, however, gives rise to a problem of too large a chip area.
Further referring to the delay circuit of
FIG. 18
, since the charge current of the capacitor
1803
is alterable by changing the number of inverting buffers used, each energized inverting buffer conducts a minimum current to charge the capacitor
1803
; for these reasons, it is difficult to reduce the charge current of the capacitor
1803
to a sufficiently low value. Even if the charge current is successfully decreased to a sufficiently low value, noise could cause the output from the delay circuit to fluctuate (change).
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problems and has an object to present a delay circuit of simple configuration that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also to present a ring oscillator incorporating the delay circuit.
A delay circuit in accordance with the present invention, in order to achieve the above object, includes: a first I
2
L inverter and a second I
2
L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters and is characterized by the following features.
The delay circuit is characterized in that it includes at least one third I
2
L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I
2
L inverter and that the third I
2
L inverter is connected to adjust a charge current of the capacitor.
In the foregoing invention, the delay refers to the time taken for the terminal voltage of the capacitor to reach the threshold voltage of the second I
2
L inverter as a result of the capacitor being charged by the current from the input of the second I
2
L inverter and is determined by the electrostatic capacitance of the capacitor.
However, a typical capacitor has a fixed electrostatic capacitance, and therefore the delay is invariable. By contrast, if the capacitor is provided external to the integrated circuit, the delay becomes variable by changing the electrostatic capacitance of the capacitor; nevertheless, the need arises to dispose the capacitor external to the integrated circuit and to equip the integrated circuit with a terminal at which the integrated circuit is coupled to the capacitor. These requirements pose serious problems in mounting of the integrated circuit.
To address this dilemma, the delay circuit includes at least one third I
2
L inverter connected to adjust a charge current of the capacitor. The provision of at least one third I
2
L inverter having an identical structure to that of the first and second I
2
L inverters enables adjustment of the charge current of the capacitor. The delay is therefore variable even if the capacitor has a fixed electrostatic capacitance. Further, the capacitor need not have a large electrostatic capacitance and therefore accounts for a reduced area in an integrated circuit; further integration of the integrated circuit is thus achieved.
The more the third I
2
L inverters, the more the electrostatic capacitance of the capacitor can be reduced.
It is preferable that the third I
2
L inverter is switchable by a control signal as to whether or not the third I
2
L inverter will contribute to adjustment of the charge current of the capacitor.
When this is the case, the third I
2
L inverter is switchable by the control signal as to whether or not the third I
2
L inverter will contribute to adjustment of the charge current of the capacitor. With two or more third I
2
L inverters provided, the amount by which the charge current of the capacitor is adjusted is variable through the control of the control signals. More precise delays therefore become available over a wider range.
It is preferable that the control signals are supplied to the third I
2
L inverters via an associated control signal input terminal of the third I
2
L inverters. When this is the case, external delay switching control becomes possible. In other words, the switching as to whether or not the third I
2
L inverter will contribute adjustment of the charge current of the capacitor is controllable by the control signal supplied to the third I
2
L inverters via the respective control signal input terminals. With two or more third I
2
L inverters provided, the charge c

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