Delay circuit and oscillator circuit using same

Details Delay circuit and oscillator circuit using same Delay circuit and oscillator circuit using same

1998-11-02

2001-02-20

Wambach, Margaret R. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S281000, C327S277000, C327S264000, C327S172000, C331S057000

Reexamination Certificate

active

06191630

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a delay circuit and to an oscillator circuit using the same. More particularly, the invention relates to a CMOS-implemented delay circuit with a variable delay time used in phase adjustment or the like, as well as to an oscillator circuit that uses this delay circuit.
CMOS delay circuits have long been in use as delay circuits for subjecting an input signal pulse to a predetermined time delay.
FIG. 22
is a diagram illustrating such a CMOS delay circuit according to the prior art. The delay circuit includes a P-MOS transistor (a P-channel field-effect transistor)
101
for supplying a charging current and having a gate terminal to which a charging control voltage
109
is applied; an N-MOS transistor (an N-channel field-effect transistor)
104
for releasing a discharge current and having a gate terminal to which a discharge control voltage
110
is applied; P-MOS and N-MOS transistors
102
and
103
constructing a CMOS inverter and having their gates connected together to provide an input terminal and their drains connected together to provide an output terminal; a charge/discharge capacitor
105
inserted between the CMOS inverter output terminal and ground potential (GND); and a discrimination circuit
106
for discriminating and comparing the capacitor terminal voltage and a predetermined threshold level and outputting a signal having a prescribed logic level in dependence upon the result of the comparison. The discrimination circuit
106
is constituted by a CMOS inverter comprising P-MOS and N-MOS transistors
107
and
108
, for example, and outputs a signal that is the result of inverting the terminal voltage level of the capacitor
105
.
The CMOS delay circuit of
FIG. 22
smoothens an input signal by the inverter circuitry, which comprises the P-MOS transistors
101
,
102
and N-MOS transistors
103
,
104
, and the capacitor
105
, and inverts the smoothened waveform by the discrimination circuit (inverter circuit)
106
comprising the P-MOS transistor
107
and N-MOS transistor
108
, thereby providing a delay.
Consider an ideal case in which the P-MOS transistor
101
and N-MOS transistor
104
are completely devoid of parasitic capacitance.
FIG. 23A
is a diagram useful in describing such an ideal case in which there is no parasitic capacitance. When the input signal is at ground level, the capacitor
105
is charged up to the power-supply level, the input to the discrimination circuit
106
is the power-supply level and the output thereof is the ground level. If the input signal rises to the power-supply level from the ground level under these conditions, the P-MOS transistor
102
turns off, the N-MOS transistor
103
turns on and the electric charge that has accumulated in the capacitor
105
is discharged through the N-MOS transistor
104
. Since the N-MOS transistor
104
acts as a current source controlled by the discharge control voltage
110
, the discharge current is rendered constant. Accordingly, the input voltage of the discrimination circuit
106
falls from the power-supply level to the ground level at a fixed slope controlled by the discharge control voltage
110
. The discrimination circuit
106
discriminates and outputs the input voltage at the threshold voltage value Vth. When the input voltage of the discrimination circuit
106
becomes Vth, therefore, the output signal level rises from the ground level to the power-supply level.
As a result of the foregoing, a delay time &tgr;
1
from the rising edge of the input signal to the rising edge of the output signal can be controlled through the slope of the input voltage of discrimination circuit
106
by the discharge control voltage
110
. Similarly, a delay time &tgr;
2
when the input signal decays can be controlled by the charging control voltage
109
.
In order for the delay circuit to operate stably, it is required that the input voltage to the discrimination circuit
106
makes a complete swing from the power-supply level to the ground level or from the ground level to the power-supply level in one period. In order for the input voltage to swing completely, the range over which delay time can be varied is limited because the slope of the input voltage to the discrimination circuit
106
is limited. In a case where the threshold voltage value Vth is one-half the power-supply voltage, the range over which the delay time can be varied is half the period T.
FIGS. 24A
,
24
B are diagrams useful in describing the reason why the input to the discrimination circuit
106
must make a complete swing.
FIG. 24A
illustrates a case where the input swings completely from the power-supply level to the ground level, and
FIG. 24B
illustrates a case where the input does not swing completely from the power-supply level to the ground level. In the case of the full swing shown in
FIG. 24A
, a delay time &tgr; is constant, i.e., is independent of the pattern of the input signal, and operation is stable. When the input to the discrimination circuit
106
does not make a full swing, however, as shown in
FIG. 24B
, the voltage at the beginning of the slope differs depending upon the input signal pattern and therefore the delay time &tgr; fluctuates (see &tgr;′, &tgr;″) depending upon the input signal and operation becomes unstable.
The foregoing relates to the ideal case in which the MOS transistors
101
,
104
are devoid of parasitic capacitance. In actuality, however, parasitic capacitances
111
,
114
exist and cause the circuit to behave in a manner different from that of the ideal case.
FIG. 23B
is a diagram useful in describing operation when the parasitic capacitances
111
,
114
exist.
When the input signal is at ground level, the capacitor
105
is charged up to the power-supply level and the input to the discrimination circuit
106
is the power-supply level. Further, the N-MOS transistor
104
is ON at all times. As a consequence, the parasitic capacitance
114
is discharged to the ground level. If the input signal rises under these conditions, the P-MOS transistor
102
turns off and the N-MOS transistor
103
turns on. As a result, the capacitor
105
and the parasitic capacitance
114
are connected in series and, hence, the input to the discrimination circuit
106
falls instantaneously to a voltage V
1
intermediate the power-supply level and the ground level until the parasitic capacitance
114
is charged. Accordingly, the input voltage to the discrimination circuit
106
subsequently starts falling from the intermediate voltage V
1
at a fixed slope controlled by the discharge control voltage
110
. Since the voltage V
1
is near the threshold voltage value Vth of the discrimination circuit
106
, the range over which the delay time can be varied cannot be enlarged.
Similarly, in a case where the input signal decays, the input voltage to the discrimination circuit
106
rises instantaneously to an intermediate voltage V
2
and then rises from the intermediate voltage V
2
at a fixed slope. As a consequence, the range over which the delay time is variable cannot be enlarged.
Thus, owing to the influence of the parasitic capacitances
111
,
114
, the input voltage to the discrimination circuit
106
changes instantaneously to the intermediate voltages V
1
, V
2
when the level of the input signal changes over, as a result of which it is not possible to enlarge the range over which delay time can be varied.
Further, since the intermediate voltages V
1
, V
2
vary depending upon the parasitic capacitances
111
,
114
, there is a great variance in delay time as caused by conditions at the time of manufacture, environmental temperature, etc.
With the conventional delay circuit, therefore, it is not possible to enlarge the range over which delay time can be varied because of the influence of the parasitic capacitance of field-effect transistors.
Further, with the conventional delay circuit, there is a great variance in delay time as caused by conditions at the time of manufacture, environmental temperature, etc.
SUMMAR

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