Delay circuit

Details Delay circuit Delay circuit

1999-10-05

2001-10-09

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000

Reexamination Certificate

active

06300813

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a delay circuit, and more particularly to, a delay circuit including delay inverters composed using p-channel and n-channel FETs (field effect transistor).
BACKGROUND OF THE INVENTION
FIG. 1
shows a conventional delay circuit. The first input of a two-input NAND gate
2
is connected to input terminal
1
. Also, to the input terminal
1
, a delay inverter (INV)
3
and a delay inverter
4
are connected in series. The second input of the NAND gate
2
is connected to the output of the delay inverter
4
. An inverter
5
is connected to the output of the NAND gate
2
, and the output of the inverter
5
is connected to output terminal
6
. The delay inverter
3
and the delay inverter
4
have a same composition, and each of them is composed of a CMOS transistor (CMOS transistor) The delay inverter
3
is composed of a p-type MOSFET (p-channel transistor, hereinafter referred to as ‘PchTr’)
3
a
and a n-type MOSFET (n-channel transistor, hereinafter referred to as ‘NchTr’)
3
b
that are connected complementarily. The delay inverter
4
is composed of a PchTr
4
a
and a NchTr
4
b
that are connected complementarily.
In the composition shown in
FIG.4
, when there is no input signal IN, “H” level signal is applied to the input terminal
1
. Signal input to the delay inverters
3
,
4
side is inverted two times, therefore “H” level signals are input to both the inputs of the NAND gate
2
. Thus, the output of the NAND gate
2
holds “L” level unalteredly. The output of the inverter
5
holds “H” level.
When input signal IN varies, i.e. a Low pulse generates, it is inverted at the inverter
3
, thereby Low pulse part is changed into High pulse as well as providing a delay of t
1
for the entire signal. This signal is further inverted and provided with a delay of t
2
at the inverter
4
, and is then applied to the second input of the NAND gate
2
. The NAND gate
2
outputs “H” level signal unless both the input signals are “H” level. Namely, from a time point at the start edge (FALL) of input signal IN to a time point at the end edge (RISE) of output signal of the inverter
4
, a “H” level signal is output from the NAND gate
2
. This signal is inverted by the inverter
5
as well as being provided with a predetermined delay time. The output signal of the inverter
5
is output from the output terminal
6
as output signal OUT with end edge (RISE) delayed at the same mode (Low pulse) as the input signal IN.
Usually, in semiconductor devices, its pulse width, timing of various signals etc. are adjusted by a delay circuit. Even when the delay amount of delay circuit is dispersed due to a variation in process, the delay circuit can operate because it is designed provided with a margin in delay amount.
However, in the conventional delay circuit, when the operating frequency becomes as high as 100 to 200 MHz, due to the margin in delay amount, a desired performance is difficult to obtain and it is therefore necessary to enhance the precision. For example, a delay circuit used for a semiconductor memory uses pulse signal to pre-charge a digit line to be subject to the reading and writing. However, when trying to get such a pulse width that can be pre-charged certainly even under a condition that the pulse width becomes shortest, i.e. a condition that the gate length L shortens or the power-source voltage VDD increases, on the contrary, the operating speed of semiconductor memory is determined according to a condition that the pulse width becomes longest. Thus, a desired characteristic cannot be obtained.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a delay circuit that the variation of delay time due to a variation in manufacturing process can be reduced.
According to the invention, a delay circuit, comprises:
a delay inverter for generating an output signal obtained by providing an input signal with a predetermined delay time;
wherein the delay inverter is composed of a p-channel FET and a n-channel FET that are connected complementarily, and one of the p-channel FET and n-channel FET is provided with a gate length elongated according to the logic of the input signal.
In this composition, paying attention to that the variation of gate length corresponds to the variation of signal pulse width, when the logic of input signal, for example, the end edge (RISE) of Low pulse needs the precision of delay time, the gate length of FET that varies from a turned-OFF state to a turned-ON state is elongated.
Thereby, the output speed is slowed, therefore the delay variation becomes small. As a result, the precision in delay time can be enhanced.
According to another aspect of the invention, a delay circuit, comprises:
a first delay inverter comprising a first p-channel FET and a first n-channel FET complementarily connected to the first p-channel FET, one of the first p-channel FET and the first n-channel FET being provided with a gate length elongated, the first p-channel FET and the first n-channel FET having gates which are connected commonly and to which input signal is applied;
a second delay inverter comprising a second p-channel FET and a second n-channel FET complementarily connected to the second p-channel FET, one of the second p-channel FET and the second n-channel FET being provided with a gate length elongated, the output of the first delay inverter being input to the second delay inverter;
a NAND gate comprising a first input to which the input signal is applied and a second input to which the output signal of the second delay inverter is applied; and
an inverter to output inverting the output signal of the NAND gate.
In this composition, both the delay inverters used in delaying are composed the complementarily-connected p-channel FET and n-channel FET, the gate of one of the FETs is designed provided with an elongated gate length L according to the logic of input signal. Paying attention to that the gate length L of FET affects the precision of delay time of delay circuit, when the logic of input signal, for example, the end edge (RISE) of Low pulse needs the precision of delay time, the gate length of FET that varies from a turned-OFF state to a turned-ON state is elongated. In detail, the gate lengths of the first n-channel FET and the second p-channel FET are elongated. Thereby, the output speed is slowed, therefore the delay variation becomes small. As a result, the precision in delay time can be enhanced.


REFERENCES:
patent: 5552719 (1996-09-01), Murakami
patent: 5663670 (1997-09-01), Idanza et al.
patent: 5731725 (1998-03-01), Rothenberger et al.
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patent: 9214306 (1997-08-01), None
patent: 9331238 (1997-12-01), None
“Horowitz And Hill: The Art of Electronics,” Paul Horowitz and Winfield Hill, Cambridge University Press 1980, p. 245.

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