Delay circuit

Details Delay circuit Delay circuit

1991-06-05

1993-07-27

Ng, Jin F.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307590, 307601, H03K 513

Patent

active

052313131

ABSTRACT:
A delay clock signal is generated by delaying an input clock signal by a predetermined time interval with a delay circuit, and is subjected to frequency division with a frequency divider circuit to generate a reference clock signal. This delay clock signal and the input clock signal are provided to a flip-flop to generate a first electronic state signal when the input clock signal turns from "High" to "Low", and a second electronic state signal when the reference clock signal turns from "High" to "Low", and to electronically activate a control object during the time the second electronic state signal is inputted.

REFERENCES:
patent: 3753126 (1973-08-01), Hines et al.
patent: 4400666 (1983-08-01), Sekiguchi
patent: 4522337 (1985-07-01), Toudo et al.
patent: 4646331 (1987-02-01), Ely
patent: 4797574 (1989-01-01), Okubo et al.
patent: 4940904 (1990-07-01), Lin
patent: 5043596 (1991-08-01), Masuda et al.

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