Delay cell and phase locked loop using the same

Details Delay cell and phase locked loop using the same Delay cell and phase locked loop using the same

2011-06-14

2011-06-14

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S274000, C327S280000, C327S287000

Reexamination Certificate

active

07961026

ABSTRACT:
A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

REFERENCES:
patent: 4792768 (1988-12-01), Fried et al.
patent: 6043719 (2000-03-01), Lin et al.
patent: 6771105 (2004-08-01), Andrasic et al.
patent: 6900703 (2005-05-01), Garvin
patent: 6943608 (2005-09-01), Kelkar
patent: 7176737 (2007-02-01), Baker et al.
patent: 7541854 (2009-06-01), Lee
patent: 10-1998-0011459 (1998-04-01), None
patent: 10-2001-0035839 (2001-05-01), None
patent: 10-0360626 (2002-11-01), None
patent: 10-2004-0072083 (2004-08-01), None
patent: 10-2005-0039247 (2005-04-01), None
patent: 10-2005-0113969 (2005-12-01), None
patent: 10-2006-0015206 (2006-02-01), None
patent: WO 99/37024 (1999-07-01), None
Korean Office Action, with English Translation, issued in Korean Patent Application No. KR 10-2007-0047499, dated May 20, 2008.
Korean Office Action issued in Korean Patent Application No. KR 10-2007-0032086 dated on Aug. 13, 2008.
Korean Office Action issued in Korean Patent Application No. KR 10-2007-0047499 dated on Aug. 19, 2008.

Affiliated with

Also associated with

Rating

Delay cell and phase locked loop using the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay cell and phase locked loop using the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay cell and phase locked loop using the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2630085