Delay adjustment circuit for delay locked loop

Details Delay adjustment circuit for delay locked loop Delay adjustment circuit for delay locked loop

2002-06-20

2004-09-14

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S263000, C327S264000

Reexamination Certificate

active

06791384

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay adjustment circuit for a delay locked loop. More particularly, the invention relates to a delay adjustment circuit for a delay locked loop, which is mainly loaded between semiconductor integrated circuits of clock synchronous types or the like, applied to a delay locked loop for synchronizing an internal clock signal used at an internal circuit based on an external control signal with an external clock signal, and provided with functions of adjusting a delay quantity of a rough interval, and adjusting a delay quantity of a fine interval.
2. Description of the Prior Art
It is a known fact that information electronic devices such as a portable telephone set have widely been used in recent years. It is also well known that many of the information electronic devices generate internal clock signals to be used at their internal circuits based on external control signals.
It is generally known that a delay locked loop (abbreviated to DLL, hereinafter) is used in order to synchronize the internal clock signals used at the internal circuits with external clock signals based on the above external control signals.
A DLL delay adjustment circuit has conventionally been provided, which is applied to the DLL for synchronizing the internal clock signals used at the internal circuits with the external clock signals based on the external control signals, and provided with functions of adjusting a delay quantity of a rough interval, and a delay quantity of a fine interval. It is well known that in this DLL delay adjustment circuit, with a higher speed and lower power consumption requested of the semiconductor integrated circuit in recent years, allowable ranges of various standards such as an output delay error (jitter) have tended to become very narrow.
FIG. 1
is a circuit block diagram schematically showing a basic configuration of a conventional DLL delay adjustment circuit.
The conventional DLL delay adjustment circuit
100
is configured by serially connecting a plurality (three in this case) of first delay elements D
1
to D
3
having maximum delay values of delay quantity adjustment of a fine interval to a selection circuit (selector) S. This conventional DLL delay adjustment circuit
100
is configured in such a manner that a second delay element FA for adjusting a delay quantity of a fine interval is connected to an output side of the selection circuit S, input clock signals CLK-IN are entered to the delay elements D
1
to D
3
, and the selection circuit S, and accordingly delay outputs obtained from the delay elements D
1
to D
3
are respectively entered to the selection circuit S.
Also, the conventional DLL delay adjustment circuit
100
is configured in such a manner that delay outputs obtained from the delay elements D
1
to D
3
are set as a delay quantity of a rough interval, first delay. control signals A
1
and A
2
for selection control are entered to the selection circuit S from an external unit, and second delay control signals B
1
, B
2
, B
3
and B
4
for setting a delay quantity of a fine interval are entered to the second delay element FA from the external unit.
In the conventional DLL delay adjustment circuit
100
, the delay quantity of a fine interval set by the second delay element FA based on the second delay control signals B
1
, B
2
, B
3
and B
4
is added to the delay quantity of a rough interval obtained as an output of roughly adjusted delays from the delay elements D
1
to D
3
selected by the selection circuit S based on the first delay control signals A
1
and A
2
, and a result of the addition can be obtained as an output clock signal CLK-OUT.
Incidentally, in the DLL delay adjustment circuit
100
, the input clock signals CLK-IN and the first delay control signals A
1
and A
2
entered to the selection circuit S can be considered as a delay quantity rough adjustment input signal system L
1
for adjusting a delay quantity of a rough interval, and the second delay control signals B
1
, B
2
, B
3
and B
4
as a delay quantity fine adjustment input signal system L
2
for adjusting a delay quantity of a fine interval.
FIG. 2
is a timing chart showing a relation of output waveforms among delay quantity adjustment of a rough interval, delay quantity adjustment of a fine interval, and a last clock total delay quantity by delay quantity adjusting operations thereof in the DLL delay adjustment circuit. It is specifically shown that when delay quantity adjustment of a fine interval is made by 0.2 ns, 1ns being a maximum, delay quantity adjustment of a rough interval is carried out as carrying of the delay quantity adjustment of a fine interval, and an output clock signal CLK-OUT is obtained by a last clock total delay quantity resulted from addition of those delay quantities.
Other conventional technologies have been presented regarding DLL delay adjustment. For example, Japanese Patent A No. 2001-56723 discloses “SEMICONDUCTOR INTEGRATED CIRCUIT”. A known technology regarding delay adjustment of a phase locked loop (called PLL) is disclosed as, for example “CONTINUOUSLY ADJUSTABLE DELAY LOCKED LOOP” in Japanese Patent A No. 11 (1999)-168376. Japanese Patent A No. 2000-323969 discloses “DIGITAL PLL APPARATUS AND DELAYLER THEREOF”. Moreover, a known technology regarding delay quantity adjustment for general high-speed digital circuit is disclosed as “DELAY ADJUSTMENT CIRCUIT” in Japanese Patent A No. 3 (1991)-35613.
However, in the case of the DLL delay adjustment circuit shown in
FIG. 1
, for example, in
FIG. 3
, if a relation between changing points of signals (obtained at input terminal names D
1
and D
2
on the selection circuit S) obtained by passing of the input clock signal CLK-IN as data at the selection circuit S through the delay elements D
1
and D
2
, and delay control signals A
2
(“01” section):A
1
(“10” section) as selection signals indicating switching operations for those signals is set in operation by a shown timing, then noise is generated in an output signal (obtained from an output terminal name Y on the section circuit S).
If the delay quantity adjustment described above with reference to
FIG. 2
is not operated normally, an output delay error similar to that shown in
FIG. 4
occurs in a last clock total delay quantity at the output clock signal CLK-OUT. That is, in
FIG. 4
, if delay quantity adjustment of a rough interval is not operated normally, when a timing of a waveform of delay quantity adjustment of a fine interval related to the delay quantity fine adjustment input signal system L
2
is shifted to be delayed from a waveform of a delay quantity adjustment of a rough interval related to the delay quantity rough adjustment input signal system L
1
(when timings of selection of the delay quantity adjustment of a fine interval and selection of the delay quantity adjustment of a rough interval are not identical to each other), the output clock signal CLK-OUT is obtained while output delay errors of 1 ns and 2 ns occur in the last clock total delay quantity.
In order to deal with the noise generated in the output of the selection circuit S and the output delay error generated in the output clock signal CLK-OUT of the delay element FA, all the delay control signals A
1
, A
2
, and B
1
to B
4
can be controlled by retiming with the output clock signal CLK-OUT. In this case, however, time for retiming must be secured in a period from the output of the selection circuit S to obtaining of the output clock signal CLK-OUT of the delay element FA. Consequently, a significant adverse effect is placed on maintenance of a high-speed operation.
In short, in the case of the conventional DLL delay adjustment circuit, because of a functional configuration, it is difficult to achieve a high-speed operation after prevention of noise generation or output delay error generation during switching by delay control signals.
SUMMARY OF THE INVENTION
An object of the present invention is to eliminate the foregoing drawbacks of the conventional art, and its techni

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