Delay adjustment circuit

Details Delay adjustment circuit Delay adjustment circuit

2002-10-15

2004-04-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S153000

Reexamination Certificate

active

06717447

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to delay adjustment circuits and, more particularly, to an improved delay adjustment circuit for synchronizing a system clock with an internal clock of a semiconductor device.
2. Related Art
Clock frequency requirements of semiconductor devices are continually increasing. This is especially true, for example, for devices such as Double Data Rate (DDR) synchronous dynamic random access memory (SDRAM) devices. It is important to synchronize an internal clock signal of a semiconductor device with a system clock signal in order to ensure accurate data communication between the device and a system. For this reason, semiconductor devices often include delay locked loops (DLLs).
A DLL facilitates synchronization of the devicc's internal clock signal with the system clock signal by compensating the internal clock signal for skew caused by gate and wiring loads. This compensation involves adjusting a delay period for the internal clock signal to minimize the phase shift between the internal clock signal and the system clock signal.
For a DDR SDRAM device, valid data is available for reading from the device in accordance with an internal clock signal that is derived from the system clock signal. The maximum number of wait cycles (column address strobe (CAS) latency) before the availability of valid data can be programmed in a mode register of the device. The maximum phase shift between the system clock signal and the internal clock signal is specified by JEDEC.
In practice, particularly in system applications, the DLL is often deactivated (“DLL off” mode) to lower device power consumption. Depending upon the device operating frequency, this deactivation can result in a large misalignment between the system clock and the internal clock. Consequently, in “DLL off” mode data may not be available for reading in accordance with JEDEC specifications, and the CAS latency may be changed from DL)R to single data rate (SDR). For example, a CAS latency of “3” indicates that data is available for reading after two clock cycles plus the data access time (t
AC
), which in “DLL off” mode may range from four to six nanoseconds.
It would be desirable to have a delay adjustment circuit for decreasing the phase shift between a system clock signal and an internal clock signal that consumes less power than a typical DLL circuit. It would be further desirable to provide a delay adjustment circuit that operates independent of system operating frequency and CAS latency.
SUMMARY
A delay adjustment circuit for a semiconductor may include a difference-pulse generator that receives a system clock signal and a feedback clock signal and provides a difference-pulse signal that indicates a phase difference between the system clock signal and the feedback clock signal, and an interim clock signal that is selected from the group comprising the feedback clock signal and an inversion of the feedback clock signal. The delay adjustment circuit may also include a delay control unit in communication with the difference-pulse generator that receives the difference-pulse signal and provides a plurality of output signals that indicate the phase difference between the system clock signal and the interim clock signal. The delay adjustment circuit may further include a delay unit in communication with the difference-pulse generator and the delay control unit that receives the interim clock signal and the plurality of output signals, and provides an internal clock signal that is in phase with the system clock signal.
The difference-pulse signal may be at logic high for a period of time that the feedback clock signal is at logic low and the system clock signal is at logic high. The interim clock signal may be the feedback clock signal.
Alternatively, the difference-pulse signal may be at logic high for a period of time that the feedback clock signal is at logic high and the system clock signal is at logic high. The interim clock signal may be an inversion of the feedback clock signal.
The delay control unit may comprise a plurality of control cells and the delay unit may comprise a plurality of delay cells. Each control cell may provide one output signal, and each delay cell may receive one output signal.
The delay unit may delay the interim clock signal by one time unit for each of the plurality of output signals that is at logic high to produce a delayed interim clock signal, and provide the delayed interim clock signal as the internal clock signal. The interim clock signal may be the feedback clock signal when the feedback clock signal is lagging the system clock signal, and it may be an inversion of the feedback clock signal when the feedback clock signal is leading the system clock signal.
The delay control unit may comprise a pulse generator that receives an enable signal, detects an edge of the enable signal, and generates a reset signal that is at logic high for a first period of time after the edge of the enable signal is detected. The first period of time may be at least a period of the system clock. The difference-pulse generator may be in communication with the pulse generator, and may receive the reset signal and provide the difference-pulse signal when the reset signal is at logic high. The difference-pulse generator may determine whether the feedback clock signal is leading the system clock signal by sampling the feedback clock signal during a rising edge of the system clock signal.
A method for adjusting the delay of an internal clock of a semiconductor include receiving a system clock signal and a feedback clock signal and generating a difference-pulse signal that indicates a phase difference between the system clock signal and the feedback clock signal. The method may also include generating an interim clock signal that is selected from the group comprising the feedback clock signal and an inversion of the feedback clock signal. The method may further include generating a plurality of output signals that indicate the phase difference between the system clock signal and the interim clock signal. The method may further include delaying the interim clock signal by an amount of time that is a function of the phase difference indicated by the plurality of output signals to produce a delayed interim clock signal. The method may additionally include providing the delayed interim clock signal as an internal clock signal.
Generating a difference-pulse signal may include generating a logic high for a period of time that the feedback clock signal is at logic low and the system clock signal is at logic high. Alternatively, generating a difference-pulse signal may include generating a logic high for a period of time that the feedback clock signal is at logic high and the system clock signal is at logic high.
Generating an interim clock signal may include inverting the feedback clock signal when the feedback clock signal is leading the system clock signal. Generating a plurality of output signals may include generating one output signal at logic high for each time unit during a period of the system clock that the system clock signal is at logic high while the interim clock signal is at logic high.
Generating a difference-pulse signal may include receiving an enable signal, detecting an edge of the enable signal, generating a reset signal that is at logic high for a first period of time after the edge of the enable signal is detected, and generating a logic low when the first period of time after the edge of the enable signal is expired.
Generating an interim clock signal may include determining whether the feedback clock signal is leading the system clock signal by sampling the feedback clock signal during a rising edge of the system clock signal, and inverting the feedback clock signal when the feedback clock signal is leading the system clock signal.
A delay adjustment circuit for a semiconductor may include a means for receiving a system clock signal and a feedback clock signal and generating a difference-pulse signal that indicates a

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