Delamination reduction between vias and conductive pads

Details Delamination reduction between vias and conductive pads Delamination reduction between vias and conductive pads

2005-02-23

2008-07-01

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S786000, C257S774000, C257S737000, C257SE23020

Reexamination Certificate

active

07394159

ABSTRACT:
Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.

REFERENCES:
patent: 5248903 (1993-09-01), Heim
patent: 5736791 (1998-04-01), Fujiki et al.
patent: 6020647 (2000-02-01), Skala et al.
patent: 6313541 (2001-11-01), Chan et al.
patent: 6534723 (2003-03-01), Asai et al.
patent: 6982487 (2006-01-01), Kim et al.
patent: 2004/0004284 (2004-01-01), Lee et al.
patent: 11-297873 (1999-10-01), None

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